1

Analog Layout Engineer Jobs in California (NOW HIRING)

Analog Layout Engineer

Santa Clara, CA ยท On-site

$237K/yr

Analog Layout Engineer Location: Santa Clara, CA (Remote Option available) Duration: Long Term Responsibilities: Senior layout designer, will be responsible for layout of high-performance analog ...

Analog Layout Engineer

San Jose, CA ยท On-site

$110K - $300K/yr

The Analog Layout Engineer will be responsible for designing and implementing analog and mixed-signal layout designs for integrated circuits. This role requires a strong understanding of analog ...

Bachelor's degree in Electrical Engineering, Electronics, or a related field. * 6+ years of hands-on experience in analog and/or RF layout design (8+ years preferred). * Proven experience with analog ...

Bachelor's degree in Electrical Engineering, Electronics, or a related field. * 6+ years of hands-on experience in analog and/or RF layout design (8+ years preferred). * Proven experience with analog ...

Staff Analog Layout Engineer

Sunnyvale, CA ยท On-site

$160K - $200K/yr

Position Overview We are seeking a seasoned Senior or Staff Analog Layout Engineer to play a vital role in developing cutting-edge full-custom electronic transceiver components that interface ...

Analog Layout Automation Engineer

San Diego, CA ยท On-site

$214K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Analog Layout Automation Engineer

San Diego, CA ยท On-site

$214K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Analog Layout Automation Engineer

Cupertino, CA ยท On-site

$249K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Analog Layout Automation Engineer

Cupertino, CA ยท On-site

$249K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Adhere to Marvell's core behaviors and strive to continuously improve your skills as an Analog Layout Engineer. * Experienced in Cadence "Virtuoso VXL" and/or Synopsys "Custom Compiler" layout tools.

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

next page

Showing results 1-20

Analog Layout Engineer information

See California salary details

$76K

$183.8K

$200.3K

How much do analog layout engineer jobs pay per year?

As of Jul 25, 2026, the average yearly pay for analog layout engineer in California is $183,800.00, according to ZipRecruiter salary data. Most workers in this role earn between $199,400.00 and $199,400.00 per year, depending on experience, location, and employer.

What are Analog Layout Engineers?

Analog Layout Engineers are specialized professionals who design the physical layout of analog and mixed-signal integrated circuits (ICs). They translate circuit schematics into detailed geometric representations that can be manufactured on silicon wafers. Their work includes placement and routing of transistors, resistors, capacitors, and interconnects, ensuring optimal performance, area, and reliability. They collaborate closely with circuit designers to meet electrical and physical requirements, and use electronic design automation (EDA) tools to create and verify layouts.

What are some common challenges Analog Layout Engineers face when collaborating with circuit designers?

Analog Layout Engineers often work closely with circuit designers to translate schematics into physical layouts, which can present challenges such as resolving conflicting design requirements or optimizing for both performance and manufacturability. Miscommunications can occur regarding layout constraints, parasitic effects, or changes in design specifications. Successful collaboration requires clear communication, proactive problem-solving, and regular design reviews to ensure that the final layout meets all electrical, physical, and timing requirements.

What are the key skills and qualifications needed to thrive as an Analog Layout Engineer, and why are they important?

To thrive as an Analog Layout Engineer, you need strong knowledge of semiconductor physics, circuit design principles, and experience with analog/mixed-signal layout, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, DRC/LVS verification tools, and familiarity with IC fabrication processes are crucial. Attention to detail, problem-solving, and effective communication are important soft skills for collaborating with design teams and ensuring design accuracy. These skills and qualities are essential for creating high-performance, manufacturable integrated circuits that meet stringent specifications and timelines.

What is the difference between Analog Layout Engineer vs Digital IC Layout Engineer?

AspectAnalog Layout EngineerDigital IC Layout Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, specialized in analog designBachelor's or Master's in Electrical Engineering, focused on digital design
Work EnvironmentDesigning analog circuits, working closely with circuit designersImplementing digital logic layouts, collaborating with digital design teams
Industry UsageSemiconductor companies, ASIC/FPGA designSemiconductor companies, ASIC/FPGA design
Common Search/ComparisonAnalog Layout Engineer vs Digital IC Layout Engineer

Both roles involve IC layout design within the semiconductor industry, but Analog Layout Engineers focus on analog circuits requiring precise analog signal handling, while Digital IC Layout Engineers work on digital logic circuits. The skills, tools, and design considerations differ, making each role specialized within the chip design process.

What are the most commonly searched types of Analog Layout Engineer jobs in California? The most popular types of Analog Layout Engineer jobs in California are:
What cities in California are hiring for Analog Layout Engineer jobs? Cities in California with the most Analog Layout Engineer job openings:
Infographic showing various Analog Layout Engineer job openings in California as of July 2026, with employment types broken down into 4% Internship, 86% Full Time, and 10% Contract. Highlights an 89% In-person, 5% Hybrid, and 6% Remote job distribution, with an average salary of $183,800 per year, or $88.4 per hour.
Analog Layout Engineer

Analog Layout Engineer

Glow Networks

Santa Clara, CA โ€ข On-site

$237K/yr

Full-time

Posted 17 days ago


Job description

Role: Analog Layout Engineer
Location: Santa Clara, CA (Remote Option available)
Duration: Long Term
Responsibilities:
Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry.
Qualifications
Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
Experience with floor planning, block level routing and top-level chip assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience with FinFET process nodes preferred
Experience working with distributed design teams a plus.
Knowledge of skill code and layout automation is a plus.
Self-starter with the ability to define and adhere to a schedule.
Must possess strong written and verbal communication skills.
10+ years' experience in high performance analog layout in advanced CMOS processes.