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Analog Layout Engineer Jobs in California (NOW HIRING)

Apple

Analog Layout Automation Engineer

Cupertino, CA · On-site

$249K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Nokia

Staff Custom Analog Layout Engineer

San Jose, CA · On-site

$139K - $258K/yr

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

Decent understanding in analog layout requirements, such as matching and shielding; * Has extensive experience in the layout of low-power, high-resolution circuits, such as SD-ADC, SAR-ADC, bandgap ...

Apple

Analog Layout Automation Engineer

Cupertino, CA

$123K - $218K/yr

  • Medical

  • Dental

  • Retirement

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

Analog Layout Automation Engineer

San Diego, CA

$118K - $207K/yr

  • Medical

  • Dental

  • Retirement

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

Analog Layout Automation Engineer

San Diego, CA

$166K - $296K/yr

  • Medical

  • Dental

  • Retirement

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

RFIC Layout Engineer

San Francisco, CA · On-site

To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and ... Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching ...

Elevate Semiconductor

Staff Analog IC Layout Engineer

San Diego, CA · On-site

$120K - $180K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The Position We are seeking a highly skilled Staff Analog Layout Engineer to join our team in developing state-of-the-art integrated circuits (ICs). In this role, you will handle the physical layout ...

Apple

Analog Layout Automation Engineer

Cupertino, CA

$175K - $311K/yr

  • Medical

  • Dental

  • Retirement

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

RFIC Layout Engineer

San Francisco, CA · On-site

To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and ... Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching ...

Elevate Semiconductor

Staff Analog IC Layout Engineer

San Diego, CA · On-site

$120K - $180K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The Position We are seeking a highly skilled Staff Analog Layout Engineer to join our team in developing state-of-the-art integrated circuits (ICs). In this role, you will handle the physical layout ...

Superbeo

Analog Layout Design Engineer

Santa Clara, CA · On-site

Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 Months, Contract to Hire * Experience with layout of cutting-edge high-performance, high-speed CMOS integrated ...

Nokia

Staff Custom Analog Layout Engineer

San Jose, CA

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

Decent understanding in analog layout requirements, such as matching and shielding; * Has extensive experience in the layout of low-power, high-resolution circuits, such as SD-ADC, SAR-ADC, bandgap ...

Neuralink

Analog IC Layout Engineer

South San Francisco, CA · On-site

$83K - $139K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art layouts for mixed-signal and analog circuits * Amplifiers * Filters * Switched capacitor circuits

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All JobsAnalog Layout Engineer JobsAnalog Layout Engineer Jobs in California

Analog Layout Engineer information

See California salary details

$76K

$183.8K

$200.3K

How much do analog layout engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for analog layout engineer in California is $183,800.00, according to ZipRecruiter salary data. Most workers in this role earn between $199,400.00 and $199,400.00 per year, depending on experience, location, and employer.

What is an analog layout engineer?

Analog Layout Engineers are specialized professionals who design the physical layout of analog and mixed-signal integrated circuits (ICs). They translate circuit schematics into detailed geometric representations that can be manufactured on silicon wafers. Their work includes placement and routing of transistors, resistors, capacitors, and interconnects, ensuring optimal performance, area, and reliability. They collaborate closely with circuit designers to meet electrical and physical requirements, and use electronic design automation (EDA) tools to create and verify layouts.

What are some common challenges analog layout engineers face when collaborating with circuit designers?

Analog Layout Engineers often work closely with circuit designers to translate schematics into physical layouts, which can present challenges such as resolving conflicting design requirements or optimizing for both performance and manufacturability. Miscommunications can occur regarding layout constraints, parasitic effects, or changes in design specifications. Successful collaboration requires clear communication, proactive problem-solving, and regular design reviews to ensure that the final layout meets all electrical, physical, and timing requirements.

What are the key skills and qualifications needed to thrive as an analog layout engineer, and why are they important?

To thrive as an Analog Layout Engineer, you need strong knowledge of semiconductor physics, circuit design principles, and experience with analog/mixed-signal layout, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, DRC/LVS verification tools, and familiarity with IC fabrication processes are crucial. Attention to detail, problem-solving, and effective communication are important soft skills for collaborating with design teams and ensuring design accuracy. These skills and qualities are essential for creating high-performance, manufacturable integrated circuits that meet stringent specifications and timelines.

What is the difference between Analog Layout Engineer vs Digital IC Layout Engineer?

AspectAnalog Layout EngineerDigital IC Layout Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, specialized in analog designBachelor's or Master's in Electrical Engineering, focused on digital design
Work EnvironmentDesigning analog circuits, working closely with circuit designersImplementing digital logic layouts, collaborating with digital design teams
Industry UsageSemiconductor companies, ASIC/FPGA designSemiconductor companies, ASIC/FPGA design
Common Search/ComparisonAnalog Layout Engineer vs Digital IC Layout Engineer

Both roles involve IC layout design within the semiconductor industry, but Analog Layout Engineers focus on analog circuits requiring precise analog signal handling, while Digital IC Layout Engineers work on digital logic circuits. The skills, tools, and design considerations differ, making each role specialized within the chip design process.

What are the most commonly searched types of Analog Layout Engineer jobs in California?

The most popular types of Analog Layout Engineer jobs in California are:

What are popular job titles related to Analog Layout Engineer jobs in California?

For Analog Layout Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Analog Layout Engineer jobs in California look for?

The top searched job categories for Analog Layout Engineer jobs in California are:

What cities in California are hiring for Analog Layout Engineer jobs?

Cities in California with the most Analog Layout Engineer job openings:

Analog Layout Engineer jobs near you
Infographic showing various Analog Layout Engineer job openings in California as of August 2026, with employment types broken down into 6% Internship, 77% Full Time, and 17% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $183,800 per year, or $88.4 per hour.

Principal Analog Layout Engineer

Marvell Technology, Inc.

San Diego, CA • On-site

Full-time

Life, Retirement

Re-posted 2 days ago

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.
This is a rare foundational engineering opportunity as part of our strategic expansion into Southern California. You will help shape the technical DNA and culture of Marvell's San Diego design organization.
What You Can Expect
  • Drawing layouts for schematics created by Circuit Design Engineers, using industry standard CAD tools, in deep sub-micron, FinFET technologies.
  • Effectively communicate with Design Engineers to clarify and realize the layout requirements based on the schematic functions.
  • Provide feedback to Circuit Design Engineers on any modifications to schematics after layouts are completed.
  • Interact with Physical Verification (PV) team to analyze DRC, LVS, ANT, ERC, and EMIR results and achieve PV closure.
  • Adhere to Marvell's core behaviors and strive to continuously improve your skills as an Analog Layout Engineer.
  • Experienced in Cadence "Virtuoso VXL" and/or Synopsys "Custom Compiler" layout tools.
  • Experienced in Mentor Graphics "Calibre" drc/lvs verification tool.
  • Good problem-solving skills.
  • Strong communication and presentation skills.
  • Ability to work independently as well as in teams, including remote design teams.
  • Ability to work across functions and levels.

What We're Looking For
  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
  • Master's degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience.
  • PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.

Expected Base Pay Range (USD)
152,300 - 225,440, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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