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Ic Layout Manager Jobs (NOW HIRING)

Neuralink

Analog IC Layout Engineer

Fremont, CA

Power management circuits * Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers * Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team ... Remote eligibility available for qualified candidates, up to managements discretion The best fit ...

Neuralink

Analog IC Layout Engineer

Fremont, CA · On-site

$83K - $139K/yr

Power management circuits * Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers * Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required ...

Skyworks

Sr. Principal IC Layout Designer

Cedar Rapids, IA · On-site

$114K - $220K/yr

Sr. Principal IC Layout Designer Posting Start Date: 5/27/26 Job Location(s): Cedar Rapids If you ... of management, and the freedom to make meaningful contributions in a setting that encourages ...

Skyworks

Sr. Principal IC Layout Designer

Cedar Rapids, IA · On-site

$114K - $220K/yr

Sr. Principal IC Layout Designer Posting Start Date: 5/27/26 Job Location(s): Cedar Rapids If you ... of management, and the freedom to make meaningful contributions in a setting that encourages ...

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How much do ic layout manager jobs pay per year?

As of Jul 5, 2026, the average yearly pay for ic layout manager in the United States is $91,454.00, according to ZipRecruiter salary data. Most workers in this role earn between $58,500.00 and $107,500.00 per year, depending on experience, location, and employer.
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Infographic showing various Ic Layout Manager job openings in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $91,454 per year, or $44 per hour.
Analog IC Layout Engineer

Analog IC Layout Engineer

Neuralink

Fremont, CA

Other

Posted 7 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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