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Ic Layout Manager Jobs (NOW HIRING)

skywater

Layout Principal Designer

Minneapolis, MN · On-site +1

This SkyWater Layout Principal Designer will primarily lead custom layout and Electronic Design ... Experience in IP project and/or library management. * Familiarity with typical mixed-signal IC ...

skywater

CAD Engineer - Staff (PDK)

Minneapolis, MN · On-site +1

... • Management of 3rd party PDK and IP developers to ensure correct collateral and accuracy ... in IC layout in Virtuoso or Allegro package design • Experience with chemical-mechanical ...

Texas Instruments

Digital IC Design Engineer

Dallas, TX · On-site

$123K/yr

... power management and analog ICs across industrial, automotive, and consumer applications. As a ... Supervise IC layout of digital blocks to ensure timing, power, and signal integrity requirements ...

Texas Instruments

Digital IC Design Engineer

Dallas, TX

$123K/yr

... power management and analog ICs across industrial, automotive, and consumer applications. As a ... Supervise IC layout of digital blocks to ensure timing, power, and signal integrity requirements ...

Synopsys

R&D Engineering, Sr Architect-17656

Sunnyvale, CA · On-site

$226K/yr

... IC design pressure, the kind where a layout decision at 3nm can make or break a tape-out schedule ... Manage maintenance and evolution of existing tool sets and infrastructure across product releases ...

SiTime Corporation

Principal Engineer, CAD

Santa Clara, CA · On-site

$164K - $226K/yr

Own PDK installation, validation, customization, maintenance and release management, ensuring ... Provide CAD Software & Linux User Support for CMOS Design Engineers & IC Layout Designers * Prepare ...

Texas Instruments

Layout Designer

Tucson, AZ · On-site

Associate's degree in Engineering or related field of study or program certificate in Advanced IC ... Strong time management skills that enable on-time project delivery About Us Why TI? * Engineer your ...

Texas Instruments

Layout Designer

Tucson, AZ

Associate's degree in Engineering or related field of study or program certificate in Advanced IC ... Strong time management skills that enable on-time project delivery About Us Why TI? * Engineer your ...

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How much do ic layout manager jobs pay per year?

As of Jul 5, 2026, the average yearly pay for ic layout manager in the United States is $91,454.00, according to ZipRecruiter salary data. Most workers in this role earn between $58,500.00 and $107,500.00 per year, depending on experience, location, and employer.
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Ic Layout Manager jobs near you
Infographic showing various Ic Layout Manager job openings in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $91,454 per year, or $44 per hour.

Layout Principal Designer

skywater

Minneapolis, MN • On-site, Remote

Other

Posted 18 days ago

Job description

This SkyWater Layout Principal Designer will primarily lead custom layout and Electronic Design Automation (EDA) activities to provide testchip collateral for semiconductor integrated circuit (IC) technologies. This engineer will be a significant contributor to a broad array of design projects supporting modeling, reliability, and yield as part of Process Design Kit (PDK) development for advanced CMOS or quantum technologies.

The position is based at our HQ site in Bloomington, MN, with consideration available for remote work.

Major Areas of Accountability:

  • Layout of new structures for eTest, modeling, reliability, yield, and IP testchips as part of new technology development
  • Version control and management of large design libraries with multiple contributors
  • Introduction of both custom and automated designs for both new & derivative layout projects supporting highly diverse technology flows
  • Utilize SkyWater PDK’s and provide feedback to internal teams on issues, improvements, capabilities, etc.
  • Lead physical verification and tape-in reviews

Required Qualifications:

  • Expert in custom layout design using IC EDA tool-assisted design flow such as Cadence and Siemens EDA tool suites, (e.g. Calibre and Virtuoso)
  • Familiarity with layout automation using SKILL, Tcl, python or other scripting languages.
  • Knowledge and experience in developing and/or using physical verification tools (DRC, ERC, LVS/PEX) and DFM tooling. 
  • Experience in IP project and/or library management.
  • Familiarity with typical mixed-signal IC design.
  • Clear communicator, concise written report skills, and inventive problem solver
  • U.S. Person Required: This position requires compliance with the International Traffic in Arms Regulations (ITAR). All accepted applicants must be U.S. Persons.
  • ITAR defines a U.S. Person as U.S. citizen, U.S. Permanent Resident, Political Asylee, or Refugee.
  • 7 - 10 years of experience with AS in Electronic Design fields. 5-7 years of experience with BS in Electrical Engineering, Microelectronics or related fields.

Preferred Qualifications:

  • Background in PDK development in some or all of the following fields: CMOS, MEMS, photonics, and superconducting.
  • Familiarity with parasitic extraction tools such as Mentor Calibre xRC, Cadence Quantus, or Synopsys StarRC.
  • Experience in project management of IC design (architecture to GDS) & fabrication (tape-out to post-silicon validation and testing).
  • Experience with chemical-mechanical polishing (CMP) shape density filling techniques.
  • Experience with data preparation and/or OPC methodologies.

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