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Ic Layout Manager Jobs (NOW HIRING)

7Rays Semiconductors

CA · On-site

· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ... Have a BSEE or equivalent experience 10+ years of custom IC layout experience, including 5+ years ...

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SpaceX

RFIC Layout Designer (RFIC Engineering)

Irvine, CA · On-site

$115K - $145K/yr

You will be an integral part of the IC design team and lead the discipline of layout at the ... Experience managing revision control systems * Experience with circuit design * Understanding of ...

The Norland Group

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Senior High Speed Mixed-Signal I/O & Analog Layout Engineer

San Jose, CA · On-site

$100 - $110/hr

... as an IC layout designer; OR 8+ years of professional experience with integrated circuit layout ... We are a strong believer of people management, professionalism and accountability. We only make ...

SpaceX

RFIC Layout Designer (RFIC Engineering)

Irvine, CA · On-site

$115K - $145K/yr

You will be an integral part of the IC design team and lead the discipline of layout at the ... Experience managing revision control systems * Experience with circuit design * Understanding of ...

Micron Technology

Staff Layout Designer

San Jose, CA · On-site

$72 - $122/hr

Contribute to group management and technical innovation * Assign resources, schedule tasks, provide ... IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and AI experience ...

Micron

Staff Layout Designer

San Jose, CA · On-site

$72 - $122/hr

Contribute to group management and technical innovation * Assign resources, schedule tasks, provide ... IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and AI experience ...

skywater

Layout Principal Designer

Minneapolis, MN · On-site +1

This SkyWater Layout Principal Designer will primarily lead custom layout and Electronic Design ... Experience in IP project and/or library management. * Familiarity with typical mixed-signal IC ...

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As of Jul 5, 2026, the average yearly pay for ic layout manager in the United States is $91,454.00, according to ZipRecruiter salary data. Most workers in this role earn between $58,500.00 and $107,500.00 per year, depending on experience, location, and employer.
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Infographic showing various Ic Layout Manager job openings in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $91,454 per year, or $44 per hour.

Sr. SRAM Layout Design Engineer

7Rays Semiconductors

CA • On-site

Other

Posted yesterday

Job description

· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.

· Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.

· Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.

· Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.

· Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.

· Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.

· Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.

· Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.

· Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Job Description

Have a BSEE or equivalent experience

10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.

Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.

Solid grasp of SRAM and memory layout principles.

Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.

Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.

Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.

Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.

Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.

Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.

Knowledge of layout automation or AI tools is a definite plus.

Apply