2

Remote Soc Design Engineer Jobs in California (NOW HIRING)

This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP ... S. preferred) degree in Electrical or Computer engineering. Tensordyne's culture was built on the ...

Staff Product Design Engineer

San Francisco, CA · On-site +1

$152K - $182K/yr

We are looking for a Staff Mechanical Design Engineer to join our hardware team working on future ... We've been alerted to scammers posing as OURA recruiters, especially for remote roles. Please note:

Cad Engineer

Arvin, CA · On-site +1

$100K - $120K/yr

Job Title: CAD Engineer We are seeking an experienced CAD Engineer with a robust background in BIM ... Work Environment This is a remote position with occasional visits to Tejon Ranch. You will work in ...

SOC Architect (Remote)

Mountain View, CA · On-site +1

$175K - $450K/yr

We are seeking an experienced System-on-Chip (SoC) Architect to lead the design of our next ... Programming/scripting skills (verilog, bash, C/C++, python etc) Compensation The US base salary for ...

SOC Architect (Remote)

Mountain View, CA · On-site +1

$175K - $450K/yr

We are seeking an experienced System-on-Chip (SoC) Architect to lead the design of our next ... Programming/scripting skills (verilog, bash, C/C++, python etc) Compensation The US base salary for ...

Staff Product Design Engineer

San Francisco, CA · On-site +1

$152K - $182K/yr

We are looking for a Staff Mechanical Design Engineer to join our hardware team working on future ... We've been alerted to scammers posing as ŌURA recruiters, especially for remote roles. Please note:

Design Engineer, Mobile

San Francisco, CA · On-site +1

$220K - $350K/yr

Without design engineers as influential voices in the company, none of this would be possible. And ... We fly remote teammates to SF for three to four days a month. Visa sponsorship. We sponsor visas:

Showing results 21-40

Remote Soc Design Engineer information

What are the most commonly searched types of Soc Design Engineer jobs in California?

The most popular types of Soc Design Engineer jobs in California are:

What are popular job titles related to Remote Soc Design Engineer jobs in California?

For Remote Soc Design Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Remote Soc Design Engineer jobs in California look for?

The top searched job categories for Remote Soc Design Engineer jobs in California are:

What cities in California are hiring for Remote Soc Design Engineer jobs?

Cities in California with the most Remote Soc Design Engineer job openings:

Infographic showing various Remote Soc Design Engineer job openings in California as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution.

Mid Level ASIC Design Engineer

Tensordyne

Sunnyvale, CA • On-site, Remote

Full-time

Medical, Life

Posted 11 days ago


Job description

About Tensordyne

Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Tensordyne is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.

About the role:

As a member of Tensordyne's ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC.This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power.

Your responsibilities will be wide-ranging and run the gamut of microarchitecture design and documentation, Verilog RTL implementation, selecting and integration 3rd-party IP blocks, working closely with design verification engineers, running frontend synthesis and working with a backend team on place-and-route guidance and timing closure.

Responsibilities:

  • Author/Understand micro-architecture specifications and participate in specification and test plan reviews.
  • Implement complex RTL designs.
  • Integrate CPU and other relevant IPs into the CPU sub-system.
  • Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.
  • Analyze code coverage and provide feedback to the verification team to achieve coverage closure.
  • Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab.

Required Qualifications:

  • 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.
  • Experience in IP integration, specifically CPU IP into SoC.
  • Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
  • Familiarity with AMBA/APB/AXI Protocol
  • Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....
  • Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.
  • Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains
  • Previous experience with timing closure at high frequencies is a plus.
  • Interest to explore AI architectures for convolution, transformer and other kinds of workloads
  • Self-starter and highly-motivated to work in a dynamic start-up environment.
  • B.S. (M.S. preferred) degree in Electrical or Computer engineering.

Tensordyne's culture was built on the following values that are equally important to us as business:

  • Put people first. We only succeed when our people succeed.
  • Ethics and integrity always; Being open, honest, and respectful of everyone.
  • Think Big. Be ambitious and have audacious goals.
  • Aim for excellence. Quality and excellence count in everything we do.
  • Own it and get it done. Results matter!
  • Make Each Person Better together than they would be as an individual.
  • Embrace each others' differences.
  • Embrace that there will be differences.

Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.