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Remote Memory Design Engineer Jobs in California

Synopsys

Memory Compiler Architect - 15954

Sunnyvale, CA · On-site +1

$226K - $338K/yr

... Category Engineering Hire Type Employee Job ID 15954 Base Salary Range $226000-$338000 Remote ... We lead in chip design, verification, and IP integration, empowering the creation of high ...

Mercor

RTL Design Engineer - AI Tools

San Francisco, CA · Remote

$100 - $175/hr

Remote Duration: 3+ months Commitment: 40 hours/week Role Responsibilities * Evaluate digital chip ... Background in CPU , GPU/ML accelerator , networking, memory subsystem, PCIe/high-speed IO , SoC ...

BuzzClan LLC

PCB Design Engineer

San Francisco, CA · Remote

Remote (Preference to California) Job Title: Core Engineering - Design Engineer V PCB Layout Engineer, AR Product Team As a PCB Layout Engineer on the AR Product Team, you will be responsible for ...

Oklo

Hot Cell Design Engineer

Santa Clara, CA · On-site +1

Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...

Oklo

Hot Cell Design Engineer

Santa Clara, CA · On-site +1

Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...

MatX

Bluespec Design Engineer

Mountain View, CA · On-site +1

$175K - $450K/yr

Build production hardware for compute, memory management, and high-speed connectivity * Develop ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

... memory management, high-speed connectivity, and other key technologies in leading-edge process ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Firecrawl

Design Engineer

San Francisco, CA · On-site +1

$160K - $240K/yr

San Francisco, CA or Remote (Americas, UTC-3 to UTC-10) Job Type: Full-Time Experience: 3+ years ... Design engineers at developer tools companies, frontend engineers with strong design instincts ...

Infotech Sourcing

Design Engineer V

Sunnyvale, CA · On-site +1

US - Remote Job Title: Core Engineering - Design Engineer V PCB Layout Engineer, AR Product Team As a PCB Layout Engineer on Meta's AR Product Team, you will be responsible for driving world-class ...

AttoTude

MMIC Design Engineer

Menlo Park, CA · Remote

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role, you will be the technical lead in the design and development of cutting-edge mixed-signal ICs. You ...

AttoTude

MMIC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role, you will be the technical lead in the design and development of cutting-edge mixed-signal ICs. You ...

PRAGMATIKE

CUDA Kernel Engineer

San Francisco, CA · Remote

Remote US Start date: ASAP Languages: English (required) About the Role Pragmatike is hiring on ... Strong ability to optimize kernels (tiling strategies, occupancy tuning, shared memory design, warp ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · On-site +1

We are looking for a Sr. ASIC Design Engineer! NVIDIA is seeking best-in-class ASIC Design ... Strong interpersonal skills and ability to work with on-site and remote teams NVIDIA is widely ...

Danaher

Consumables Design Engineer II

Sunnyvale, CA · On-site +1

$93K - $128K/yr

The Consumables Design Engineer is responsible for designing, testing, and validating new ... We recognize the benefits of flexible, remote working arrangements for eligible roles and are ...

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All JobsMemory Design Engineer JobsRemote Memory Design Engineer JobsRemote Memory Design Engineer Jobs in California

Remote Memory Design Engineer information

What is the difference between Remote Memory Design Engineer vs Memory Architect?

AspectRemote Memory Design EngineerMemory Architect
CredentialsBachelor's or Master's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; often with specialized certifications
Work EnvironmentDesign teams, R&D labs, semiconductor companies, often collaborative and project-basedHigh-level planning, system-level design, often in R&D or architecture teams
Industry UsageUsed in semiconductor, electronics, and hardware development companiesPrimarily in chip design, hardware architecture firms, and large tech companies

The Remote Memory Design Engineer focuses on designing and optimizing memory components at the circuit level, while the Memory Architect develops overall memory system architectures and strategies. Both roles require strong technical skills, but the Design Engineer is more hands-on with hardware implementation, whereas the Architect works on high-level design and system integration.

What are the key skills and qualifications needed to thrive as a Remote Memory Design Engineer, and why are they important?

To thrive as a Remote Memory Design Engineer, you need a solid understanding of digital circuit design, semiconductor memory architecture, and a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence and Synopsys, as well as experience with hardware description languages such as Verilog or VHDL, are typically required. Strong problem-solving abilities, attention to detail, and effective remote communication skills set outstanding candidates apart. These skills ensure the ability to design reliable, high-performance memory circuits while collaborating efficiently with distributed teams.

What are some common challenges faced by remote memory design engineers, and how can they be addressed?

Remote memory design engineers often encounter challenges such as collaborating effectively with globally distributed teams, managing complex hardware-software integration remotely, and ensuring clear communication on intricate design specifications. These obstacles can be addressed by leveraging collaborative design tools, participating in regular virtual meetings, and maintaining thorough documentation to align with team members. Proactive communication and strong organizational skills are crucial for staying synchronized with project milestones and quickly resolving technical issues.

What does a Remote Memory Design Engineer do?

A Remote Memory Design Engineer is responsible for designing and developing memory components, such as DRAM, SRAM, or Flash, used in electronic devices and systems. Working remotely, they collaborate with hardware and software teams to optimize memory performance, power consumption, and reliability. Their work often includes circuit design, simulation, validation, and troubleshooting. They also stay updated on the latest memory technologies and may contribute to documentation and technical support.
What are the most commonly searched types of Memory Design Engineer jobs in California? The most popular types of Memory Design Engineer jobs in California are:
What are popular job titles related to Remote Memory Design Engineer jobs in California? For Remote Memory Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Remote Memory Design Engineer jobs in California look for? The top searched job categories for Remote Memory Design Engineer jobs in California are:
What cities in California are hiring for Remote Memory Design Engineer jobs? Cities in California with the most Remote Memory Design Engineer job openings:
Remote Memory Design Engineer jobs near you
Infographic showing various Remote Memory Design Engineer job openings in California as of June 2026, with employment types broken down into 50% Full Time, 33% Part Time, and 17% Contract. Highlights an 100% Remote job distribution.

Lead ASIC RTL Design Engineer

4 Staffing Corp - Client Jobs

San Francisco, CA • On-site, Remote

$170K - $250K/yr

Full-time

Posted 25 days ago

Job description

Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship

Role Summary
Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership of key IP blocks from early architectural definition through RTL delivery and signoff, working closely with cross-functional teams to meet aggressive performance, power, and area goals. The role combines hands-on design work with technical leadership and mentorship.

Core Responsibilities

Architecture & RTL Development

  • Define microarchitecture for complex subsystems and document design specifications
  • Implement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent
  • Incorporate assertions and design-for-debug features within RTL

Design Ownership & Implementation

  • Lead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness
  • Collaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs
  • Take responsibility for achieving performance, power, and area (PPA) targets for assigned blocks

High-Speed Interfaces & Memory Systems

  • Design and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics)
  • Work on memory subsystem integration, including external DRAM and high-throughput memory solutions
  • Coordinate with internal teams and third-party IP providers to ensure proper integration and functionality

Engineering Processes & Tooling

  • Establish and maintain RTL design standards, reusable components, and signoff criteria
  • Contribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines)

Collaboration & System Integration

  • Partner with verification teams on test planning, coverage goals, and model alignment
  • Work with architecture and performance engineering to validate design intent against system-level expectations
  • Support silicon bring-up, debugging, and downstream customer or system integration efforts

Technical Leadership

  • Mentor less experienced engineers and provide guidance on design best practices
  • Lead design reviews and help drive key technical decisions across teams
  • Advocate for scalable, efficient, and high-quality engineering solutions

Basic Qualifications

  • Bachelor's or Master's degree in Electrical or Computer Engineering (or similar field)
  • 8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices
  • Demonstrated experience delivering designs from concept through RTL implementation and tape out readiness
  • Strong System Verilog expertise, including clocking strategies, reset design, and domain crossing considerations
  • Hands-on experience with front-end design tools and flows (linting, CDC analysis, synthesis, timing analysis, DFT)
  • Familiarity with multiple high-speed technologies such as memory interfaces, interconnect protocols, or compute data paths
  • Strong communication skills with the ability to lead technical discussions and document designs clearly

Preferred Experience

  • Exposure to AI/ML hardware or high-performance compute architectures
  • Knowledge of formal verification techniques and assertion-based design
  • Experience with power optimization methods (e.g., clock gating, power intent formats like UPF/CPF)
  • Familiarity working alongside verification environments (UVM, Python-based frameworks, or similar)
  • Understanding of modern processor subsystems, coherence models, or custom tool flows