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Remote Memory Design Engineer Jobs in California

Remote Duration: 3+ months Commitment: 40 hours/week Role Responsibilities * Evaluate digital chip ... Background in CPU , GPU/ML accelerator , networking, memory subsystem, PCIe/high-speed IO , SoC ...

Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...

Bluespec Design Engineer

Mountain View, CA · On-site +1

$175K - $450K/yr

Build production hardware for compute, memory management, and high-speed connectivity * Develop ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...

Design Engineer

San Francisco, CA · On-site +1

$160K - $240K/yr

San Francisco, CA or Remote (Americas, UTC-3 to UTC-10) Job Type: Full-Time Experience: 3+ years ... Design engineers at developer tools companies, frontend engineers with strong design instincts ...

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

... memory management, high-speed connectivity, and other key technologies in leading-edge process ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

US - Remote Job Title: Core Engineering - Design Engineer V PCB Layout Engineer, AR Product Team As a PCB Layout Engineer on Meta's AR Product Team, you will be responsible for driving world-class ...

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role, you will be the technical lead in the design and development of cutting-edge mixed-signal ICs. You ...

MMIC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role, you will be the technical lead in the design and development of cutting-edge mixed-signal ICs. You ...

Design Engineer V

Sunnyvale, CA · On-site +1

$125 - $130/hr

US remote - Onsite work is a possibility, with a strong preference for Sunnyvale, California PCB ... Design Traveler document. Create and modify engineering tool project templates, meta-data ...

We are looking for a Sr. ASIC Design Engineer! NVIDIA is seeking best-in-class ASIC Design ... Strong interpersonal skills and ability to work with on-site and remote teams NVIDIA is widely ...

Consumables Design Engineer II

Sunnyvale, CA · On-site +1

$93K - $128K/yr

The Consumables Design Engineer is responsible for designing, testing, and validating new ... We recognize the benefits of flexible, remote working arrangements for eligible roles and are ...

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Showing results 1-20

Remote Memory Design Engineer information

What is the difference between Remote Memory Design Engineer vs Memory Architect?

AspectRemote Memory Design EngineerMemory Architect
CredentialsBachelor's or Master's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; often with specialized certifications
Work EnvironmentDesign teams, R&D labs, semiconductor companies, often collaborative and project-basedHigh-level planning, system-level design, often in R&D or architecture teams
Industry UsageUsed in semiconductor, electronics, and hardware development companiesPrimarily in chip design, hardware architecture firms, and large tech companies

The Remote Memory Design Engineer focuses on designing and optimizing memory components at the circuit level, while the Memory Architect develops overall memory system architectures and strategies. Both roles require strong technical skills, but the Design Engineer is more hands-on with hardware implementation, whereas the Architect works on high-level design and system integration.

What are the key skills and qualifications needed to thrive as a Remote Memory Design Engineer, and why are they important?

To thrive as a Remote Memory Design Engineer, you need a solid understanding of digital circuit design, semiconductor memory architecture, and a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence and Synopsys, as well as experience with hardware description languages such as Verilog or VHDL, are typically required. Strong problem-solving abilities, attention to detail, and effective remote communication skills set outstanding candidates apart. These skills ensure the ability to design reliable, high-performance memory circuits while collaborating efficiently with distributed teams.

What are some common challenges faced by remote memory design engineers, and how can they be addressed?

Remote memory design engineers often encounter challenges such as collaborating effectively with globally distributed teams, managing complex hardware-software integration remotely, and ensuring clear communication on intricate design specifications. These obstacles can be addressed by leveraging collaborative design tools, participating in regular virtual meetings, and maintaining thorough documentation to align with team members. Proactive communication and strong organizational skills are crucial for staying synchronized with project milestones and quickly resolving technical issues.

What does a Remote Memory Design Engineer do?

A Remote Memory Design Engineer is responsible for designing and developing memory components, such as DRAM, SRAM, or Flash, used in electronic devices and systems. Working remotely, they collaborate with hardware and software teams to optimize memory performance, power consumption, and reliability. Their work often includes circuit design, simulation, validation, and troubleshooting. They also stay updated on the latest memory technologies and may contribute to documentation and technical support.
What are the most commonly searched types of Memory Design Engineer jobs in California? The most popular types of Memory Design Engineer jobs in California are:
What cities in California are hiring for Remote Memory Design Engineer jobs? Cities in California with the most Remote Memory Design Engineer job openings:
Infographic showing various Remote Memory Design Engineer job openings in California as of July 2026, with employment types broken down into 87% Full Time, 9% Part Time, 1% Temporary, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution.
Principal Software Engineer - Large-Scale LLM Memory and Storage Systems

Principal Software Engineer - Large-Scale LLM Memory and Storage Systems

Nvidia

Santa Clara, CA • On-site, Remote

$158K - $212K/yr

Full-time

Posted 16 days ago


Job description

NVIDIA Dynamo is a high-throughput, low-latency inference framework for serving generative AI and reasoning models across multi-node distributed environments. Built in Rust for performance and Python for extensibility, Dynamo orchestrates GPU shards, routes requests, and manages shared KV cache across heterogeneous clusters so that many accelerators feel like a single system at datacenter scale. As large language models rapidly outgrow the memory and compute budget of any single GPU, this platform enables efficient, resilient deployment of cutting-edge LLM workloads.


We are seeking a Principal Systems Engineer to define the vision and roadmap for memory management of large-scale LLM and storage systems.


What you'll be doing:

  • Design and evolve a unified memory layer that spans GPU memory, pinned host memory, RDMA-accessible memory, SSD tiers, and remote file/object/cloud storage to support large-scale LLM inference.

  • Architect and implement deep integrations with leading LLM serving engines (such as vLLM, SGLang, TensorRT-LLM), with a focus on KV-cache offload, reuse, and remote sharing across heterogeneous and disaggregated clusters.

  • Co-design interfaces and protocols that enable disaggregated prefill, peer-to-peer KV-cache sharing, and multi-tier KV-cache storage (GPU, CPU, local disk, and remote memory) for high-throughput, low-latency inference.

  • Partner closely with GPU architecture, networking, and platform teams to exploit GPUDirect, RDMA, NVLink, and similar technologies for low-latency KV-cache access and sharing across heterogeneous accelerators and memory pools.

  • Mentor senior and junior engineers, set technical direction for memory and storage subsystems, and represent the team in internal reviews and external forums (open source, conferences, and customer-facing technical deep dives).

What we need to see:

  • Masters or PhD or equivalent experience

  • 15+ years of experience building large-scale distributed systems, high-performance storage, or ML systems infrastructure in C/C++ and Python, with a track record of delivering production services.

  • Deep understanding of memory hierarchies (GPU HBM, host DRAM, SSD, and remote/object storage) and experience designing systems that span multiple tiers for performance and cost efficiency.

  • Distributed caching or key-value systems, especially designs optimized for low latency and high concurrency.

  • Hands-on experience with networked I/O and RDMA/NVMe-oF/NVLink-style technologies, and familiarity with concepts like disaggregated and aggregated deployments for AI clusters.

  • Strong skills in profiling and optimizing systems across CPU, GPU, memory, and network, using metrics to drive architectural decisions and validate improvements in TTFT and throughput.

  • Excellent communication skills and prior experience leading cross-functional efforts with research, product, and customer teams.

Ways to stand out from the crowd:

  • Prior contributions to open-source LLM serving or systems projects focused on KV-cache optimization, compression, streaming, or reuse.

  • Experience designing unified memory or storage layers that expose a single logical KV or object model across GPU, host, SSD, and cloud tiers, especially in enterprise or hyperscale environments.

  • Publications or patents in areas such as LLM systems, memory-disaggregated architectures, RDMA/NVLink-based data planes, or KV-cache/CDN-like systems for ML.

With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to outstanding growth, our special engineering teams are growing fast. If you're a creative and autonomous engineer with a genuine passion for technology, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 272,000 USD - 431,250 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until January 13, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Nvidia logo

About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993