2

Remote Memory Design Engineer Jobs in California

Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory ... Familiarity with low power design. UPF flow for defining power intent of chips with multiple power ...

Staff RFIC Design Engineer

San Jose, CA · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... Experience supporting remote engineering teams. * Be able to work independently, communicate well ...

Design Engineer, Mobile

San Francisco, CA · On-site +1

$220K - $350K/yr

Without design engineers as influential voices in the company, none of this would be possible. And ... We fly remote teammates to SF for three to four days a month. Visa sponsorship. We sponsor visas:

Electronics Design Engineer

Fremont, CA · On-site +1

$110K - $150K/yr

Ideally located in the Northern California or Washington State (Remote options available within the ... Use this insight to help streamline engineering efforts to adapt our offerings and remain ...

We are looking for a Senior Mechanical Design Engineer to join our hardware team working on future ... We've been alerted to scammers posing as OURA recruiters, especially for remote roles. Please note:

We are seeking an IC Design Engineer to work on the development of integrated Phase-Locked Loops ... A temporary remote work exception is approved while our Bay Area and San Diego sites are being ...

We are headquartered in Los Angeles, CA with both a local and remote team. We were founded and ... Analyze code for performance and optimization opportunities as it relates to load times, memory ...

EDA / CAD Engineer

Palo Alto, CA · Remote

$150K - $260K/yr

Remote computing support experience (ETX) * Experience supporting engineering across multiple ... CAD workflows. * CI/CD & regression infrastructure: Jenkins, GitLab CI/CD, GitHub Actions ...

New

We are looking for a Senior Mechanical Design Engineer to join our hardware team working on future ... We've been alerted to scammers posing as ŌURA recruiters, especially for remote roles. Please note:

Showing results 21-40

Remote Memory Design Engineer information

What does a remote memory design engineer do?

A Remote Memory Design Engineer is responsible for designing and developing memory components, such as DRAM, SRAM, or Flash, used in electronic devices and systems. Working remotely, they collaborate with hardware and software teams to optimize memory performance, power consumption, and reliability. Their work often includes circuit design, simulation, validation, and troubleshooting. They also stay updated on the latest memory technologies and may contribute to documentation and technical support.

What are the key skills and qualifications needed to thrive as a remote memory design engineer, and why are they important?

To thrive as a Remote Memory Design Engineer, you need a solid understanding of digital circuit design, semiconductor memory architecture, and a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence and Synopsys, as well as experience with hardware description languages such as Verilog or VHDL, are typically required. Strong problem-solving abilities, attention to detail, and effective remote communication skills set outstanding candidates apart. These skills ensure the ability to design reliable, high-performance memory circuits while collaborating efficiently with distributed teams.

What are some common challenges faced by remote memory design engineers, and how can they be addressed?

Remote memory design engineers often encounter challenges such as collaborating effectively with globally distributed teams, managing complex hardware-software integration remotely, and ensuring clear communication on intricate design specifications. These obstacles can be addressed by leveraging collaborative design tools, participating in regular virtual meetings, and maintaining thorough documentation to align with team members. Proactive communication and strong organizational skills are crucial for staying synchronized with project milestones and quickly resolving technical issues.

What is the difference between Remote Memory Design Engineer vs Memory Architect?

AspectRemote Memory Design EngineerMemory Architect
CredentialsBachelor's or Master's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; often with specialized certifications
Work EnvironmentDesign teams, R&D labs, semiconductor companies, often collaborative and project-basedHigh-level planning, system-level design, often in R&D or architecture teams
Industry UsageUsed in semiconductor, electronics, and hardware development companiesPrimarily in chip design, hardware architecture firms, and large tech companies

The Remote Memory Design Engineer focuses on designing and optimizing memory components at the circuit level, while the Memory Architect develops overall memory system architectures and strategies. Both roles require strong technical skills, but the Design Engineer is more hands-on with hardware implementation, whereas the Architect works on high-level design and system integration.

What are the most commonly searched types of Memory Design Engineer jobs in California?

The most popular types of Memory Design Engineer jobs in California are:

What are popular job titles related to Remote Memory Design Engineer jobs in California?

For Remote Memory Design Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Remote Memory Design Engineer jobs in California look for?

The top searched job categories for Remote Memory Design Engineer jobs in California are:

What cities in California are hiring for Remote Memory Design Engineer jobs?

Cities in California with the most Remote Memory Design Engineer job openings:

Infographic showing various Remote Memory Design Engineer job openings in California as of August 2026, with employment types broken down into 78% Full Time, 13% Part Time, and 9% Contract. Highlights an 100% Remote job distribution.

Senior ASIC Design Engineer

Cornelis Networks

San Jose, CA • On-site, Remote

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted yesterday


Key responsibilities

  • Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.

  • Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.

  • Support post-silicon validation by working with hardware, firmware, and software teams to debug and resolve ASIC issues.


Job description

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.


Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions.

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.


Cornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols-including TCP/IP, RDMA/RoCE, and IPSec-and their application in high-speed data processing and networking environments.


Key Responsibilities:

  • Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
  • Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
  • Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
  • Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
  • Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.


MinimumQualifications:

  • B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
  • 8+ years of post-college experience in digital design with proficiency in Verilog and System Verilog.
  • Experience in RTL design for high-speed data paths or packet processing in ASICs.
  • Deep understanding of Host Ethernet adaptor architectures.
  • Familiarity with timing closure and modern physical design methodologies.
  • Proven ability in system-level debug and root cause analysis of technical issues.
  • Strong verbal and written communication skills.


Preferred Qualifications:

  • Knowledge of Ethernet architecture and networking protocols.
  • Prior experience with RTL development for Ethernet host adapters and system debug.
  • Expertise in multiple clock domain designs and asynchronous interfaces.
  • 5+ years of experience with scripting languages such as TCL, Python, or Perl.
  • Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime.


Location: This is a remote position for employees residing within the United States.


We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.

In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.