Suwanee, GA · Hybrid
$126K/yr
Role Overview We are seeking an experienced Verification Engineer to design and develop system-level UVM testbenches for advanced memory and interconnect products, including DDR5 DIMMs, Power ...
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Suwanee, GA · Hybrid
$126K/yr
Role Overview We are seeking an experienced Verification Engineer to design and develop system-level UVM testbenches for advanced memory and interconnect products, including DDR5 DIMMs, Power ...
Suwanee, GA · Hybrid
$150K - $225K/yr
Senior Verification Engineer Also open to staff, principal, or senior principal level engineers ... Developing, driving, and implementing UVM SystemVerilog TestBench infrastructure * Developing ...
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Suwanee, GA · Hybrid
$150K - $225K/yr
Senior Verification Engineer Also open to staff, principal, or senior principal level engineers ... Developing, driving, and implementing UVM SystemVerilog TestBench infrastructure * Developing ...
Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Participate in feasibility studies.
Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Participate in feasibility studies.
Duluth, GA · On-site
$125K/yr
... UVM methodology • Support in developing verification plan based on specifications. • Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker ...
Duluth, GA · On-site
$125K/yr
... UVM methodology • Support in developing verification plan based on specifications. • Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker ...
... UVM methodology · Support in developing verification plan based on specifications. · Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker ...
Quick apply
... UVM methodology · Support in developing verification plan based on specifications. · Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker ...
Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Key Responsibilities Drive the Memory interface ...
Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Key Responsibilities Drive the Memory interface ...
Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Key Responsibilities Drive the Memory interface ...
Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Key Responsibilities Drive the Memory interface ...
Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Key Responsibilities Drive the Memory interface ...
Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Key Responsibilities Drive the Memory interface ...
... using UVM methodology. • Participate in feasibility studies. • Support in developing verification plan based on specifications. • Support in Verification planning, maintenance, feature ...
... using UVM methodology. • Participate in feasibility studies. • Support in developing verification plan based on specifications. • Support in Verification planning, maintenance, feature ...
$159K/yr
Familiarity with verification methodologies (UVM is a plus) * Strong problem-solving skills and ability to work across disciplines * Must be willing to work full-time, onsite, in Atlanta, GA.
$159K/yr
Familiarity with verification methodologies (UVM is a plus) * Strong problem-solving skills and ability to work across disciplines * Must be willing to work full-time, onsite, in Atlanta, GA.
Atlanta, GA · On-site
$159K/yr
Familiarity with verification methodologies (UVM is a plus) * Strong problem-solving skills and ability to work across disciplines * Must be willing to work full-time, onsite, in Atlanta, GA.
Atlanta, GA · On-site
$159K/yr
Familiarity with verification methodologies (UVM is a plus) * Strong problem-solving skills and ability to work across disciplines * Must be willing to work full-time, onsite, in Atlanta, GA.
Atlanta, GA · On-site
$159K/yr
Familiarity with verification methodologies (UVM is a plus) * Strong problem-solving skills and ability to work across disciplines * Must be willing to work full-time, onsite, in Atlanta, GA.
Quick apply
Atlanta, GA · On-site
$159K/yr
Familiarity with verification methodologies (UVM is a plus) * Strong problem-solving skills and ability to work across disciplines * Must be willing to work full-time, onsite, in Atlanta, GA.
$67.6K - $77K
1% of jobs
$77K - $86.5K
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$111.1K is the 25th percentile. Wages below this are outliers.
$105.5K - $115K
35% of jobs
The median wage is $116.8K / yr.
$115K - $124.4K
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$67.6K
$120.4K
$171.8K
To thrive as a UVM Verification engineer, you need a solid background in digital design fundamentals, SystemVerilog, and deep expertise in the Universal Verification Methodology (UVM), often backed by a degree in Electrical or Computer Engineering. Familiarity with simulation tools such as Mentor Questa or Synopsys VCS, as well as version control systems and UVM-specific certifications, is highly valuable. Strong analytical abilities, attention to detail, teamwork, and effective communication are important soft skills in this field. These competencies ensure robust, efficient verification of complex hardware designs, leading to higher product quality and successful project outcomes.
As a UVM Verification engineer, your day-to-day tasks generally include developing test benches, writing and executing test cases, analyzing simulation results, and debugging issues using UVM methodologies. You'll collaborate closely with design engineers to understand specifications and verify that the hardware operates as intended, and you may also contribute to code reviews and continuous integration processes. In addition to technical development, regular meetings for planning, status updates, and issue resolution are common. This role offers opportunities to mentor junior team members and stay up to date with the latest verification techniques and tools, fostering both team and personal growth.
A UVM Verification job involves verifying the functionality of digital hardware designs using the Universal Verification Methodology (UVM). Engineers in this role create testbenches, write SystemVerilog code, and develop constrained-random and directed tests to validate chip designs. They work closely with design teams to find and debug issues before fabrication, ensuring high-quality and reliable silicon. UVM verification is essential in industries like semiconductors, automotive, and communications to meet performance and reliability standards.
Senior Verification Engineer (DDR5 / PMIC / CXL)
Johns Creek, GA (Hybrid/Onsite)
About the Opportunity
Our client, a growing semiconductor organization, has recently expanded its U.S. footprint in the Atlanta area. This is a unique opportunity to join a high-performing engineering team focused on next-generation memory and interconnect solutions supporting data center and cloud infrastructure.
The role offers strong ownership, hands-on technical impact, and meaningful growth within a collaborative global environment.
Role Overview
We are seeking an experienced Verification Engineer to design and develop system-level UVM testbenches for advanced memory and interconnect products, including DDR5 DIMMs, Power Management ICs (PMIC), and CXL-based solutions.
This individual will play a key role in building verification infrastructure, driving system and IP validation, and collaborating across global engineering teams.
Key Responsibilities
Develop and implement UVM/SystemVerilog testbenches for system-level and IP verification
Build verification infrastructure, including stimulus, coverage models, assertions, and scripts
Perform functional verification for memory subsystem and mixed-signal components
Collaborate with design, product, and specification engineering teams
Partner with global verification teams across multiple sites
Debug failing simulations and regression issues
Participate in silicon debug and bring-up activities as needed
Mentor and guide junior engineers
Required Qualifications
BS or MS in Electrical Engineering, Computer Engineering, or related field
5+ years of verification experience in semiconductor environments
Strong hands-on experience building UVM testbenches from scratch
Proficiency with tools such as VCS, Xcelium, Verdi, or similar
Experience with mixed-signal or digital verification methodologies
Solid debugging and problem-solving skills
Preferred Qualifications
Knowledge of DDR5 protocol and/or CXL 2.0 specification
Experience with PMIC or memory subsystem verification
Familiarity with CMOS circuit design fundamentals
Why This Role
Work on cutting-edge memory and interconnect technologies
High visibility and ownership within engineering programs
Collaborative, global team environment
Strong opportunity for career advancement
