$134.80K - $164.50K/yr
Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...
$134.80K - $164.50K/yr
Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...
$134.80K - $164.50K/yr
Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...
$134.80K - $164.50K/yr
Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...
$134.80K/yr
Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM. * Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
$134.80K/yr
Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM. * Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
Costa Mesa, CA · On-site
$145.90K - $178.10K/yr
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...
Costa Mesa, CA · On-site
$145.90K - $178.10K/yr
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...
UVM and System Verilog Requirement: . 5+ or more years of proven experience on ASIC / SoC / IP Verification. Strong experience in SystemVerilog and UVM verification methodologies Proficiency in ...
UVM and System Verilog Requirement: . 5+ or more years of proven experience on ASIC / SoC / IP Verification. Strong experience in SystemVerilog and UVM verification methodologies Proficiency in ...
Austin, TX · On-site
$134.80K - $164.50K/yr
Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...
Austin, TX · On-site
$134.80K - $164.50K/yr
Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...
Costa Mesa, CA · On-site
$145.90K - $178.10K/yr
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...
Costa Mesa, CA · On-site
$145.90K - $178.10K/yr
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...
Santa Clara, CA · On-site
$159.70K/yr
Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM. * Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
Santa Clara, CA · On-site
$159.70K/yr
Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM. * Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
Costa Mesa, CA · On-site
$145.90K - $178.10K/yr
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...
Costa Mesa, CA · On-site
$145.90K - $178.10K/yr
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...
$159.70K/yr
Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM. * Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
$159.70K/yr
Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM. * Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
Costa Mesa, CA · On-site
$145.90K - $178.10K/yr
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...
Costa Mesa, CA · On-site
$145.90K - $178.10K/yr
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...
UVM and System Verilog Requirement: . • 5+ or more years of proven experience on ASIC / SoC / IP Verification. • Strong experience in SystemVerilog and UVM verification methodologies • ...
UVM and System Verilog Requirement: . • 5+ or more years of proven experience on ASIC / SoC / IP Verification. • Strong experience in SystemVerilog and UVM verification methodologies • ...
UVM and System Verilog Requirement: . 5+ or more years of proven experience on ASIC / SoC / IP Verification. Strong experience in SystemVerilog and UVM verification methodologies Proficiency in ...
UVM and System Verilog Requirement: . 5+ or more years of proven experience on ASIC / SoC / IP Verification. Strong experience in SystemVerilog and UVM verification methodologies Proficiency in ...
Santa Clara, CA · On-site
$159.70K - $195K/yr
Santa Clara, CA/On-Site Long Term Mandatory Areas Must Have Skills - FPGA Verification Engineer Skill 1 - 8 + Years of in FPGA Skill 2 - 5 +Years of Exp in UVM Skill 2 - 5 +Years of Exp in System ...
Santa Clara, CA · On-site
$159.70K - $195K/yr
Santa Clara, CA/On-Site Long Term Mandatory Areas Must Have Skills - FPGA Verification Engineer Skill 1 - 8 + Years of in FPGA Skill 2 - 5 +Years of Exp in UVM Skill 2 - 5 +Years of Exp in System ...
San Diego, CA · On-site
$144.40K - $176.20K/yr
Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll ...
San Diego, CA · On-site
$144.40K - $176.20K/yr
Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll ...
Chandler, AZ · On-site
$198.90K/yr
Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow * Contribute to development of automation tools for design, verification and modeling ...
Chandler, AZ · On-site
$198.90K/yr
Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow * Contribute to development of automation tools for design, verification and modeling ...
Los Altos, CA · On-site
$160.80K/yr
... UVM verification environments * C/C++ expertise * Excellent communication skills and a strong track record of cross-functional collaboration * Must have Experience with and understanding of common ...
Los Altos, CA · On-site
$160.80K/yr
... UVM verification environments * C/C++ expertise * Excellent communication skills and a strong track record of cross-functional collaboration * Must have Experience with and understanding of common ...
$172.39K - $199.23K/yr
Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity. SystemVerilog Assertion for Dynamic and Formal ...
$172.39K - $199.23K/yr
Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity. SystemVerilog Assertion for Dynamic and Formal ...
San Diego, CA · On-site
$144.40K - $176.20K/yr
Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll ...
San Diego, CA · On-site
$144.40K - $176.20K/yr
Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll ...
San Jose, CA · On-site
$149.10K - $215K/yr
Create testcase and testbench with UVM methodology * Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification
San Jose, CA · On-site
$149.10K - $215K/yr
Create testcase and testbench with UVM methodology * Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification
$80K - $91.2K
1% of jobs
$91.2K - $102.5K
1% of jobs
$102.5K - $113.7K
1% of jobs
$113.7K - $124.9K
1% of jobs
$131.5K is the 25th percentile. Wages below this are outliers.
$124.9K - $136.1K
35% of jobs
The median wage is $138.3K / yr.
$136.1K - $147.4K
54% of jobs
$147.4K - $158.6K
1% of jobs
$158.6K - $169.8K
1% of jobs
$169.8K - $181K
2% of jobs
$181K - $192.3K
1% of jobs
$192.3K - $203.5K
1% of jobs
$80K
$142.6K
$203.5K
$134.80K - $164.50K/yr
Other
Medical, Retirement
Posted 15 days ago
Senior Design Verification Engineer
Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you.
Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates for this role will support verification of advanced CPU/GPU based SOCs.
Correct Designs is NOT the typical contracting, staff augmentation firm. Our engineers have respected long term roles with generous hourly rates in excellent team environments. A typical contract may last 3 years, although we have shorter and even longer term work available. We are well respected in the Design Verification community with clients always seeking new CDI engineers. If you need a few months off between contracts you can take that break and know there will be plenty of work available when you return. If you like the stability of always working, simply move to the next contract with little time off. Correct Designs does provide health care and retirement plan benefits.
We are based in Austin, Texas with clients throughout the US. There are opportunities for both in-person and remote work.
Whether you are an experienced veteran looking for new challenges, or a talented engineer seeking to broaden your experience, we can offer exciting options for your career.
Correct Designs uses E-Verify to confirm work status eligibility.
RESPONSIBILITIES:
REQUIRED SKILLS AND EXPERIENCE:
DESIRED SKILLS:
EDUCATION:
Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science
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Sourced by ZipRecruiter
11 - 50 Employees
Austin, TX, US
1999
