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Formal Verification Jobs in Dallas, TX (NOW HIRING)

Purple Hires Inc

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress ...

Ams Osram

Senior Staff Digital Design Engineer

Plano, TX · On-site

$120 - $180/hr

Drive design quality and signoff through Lint, CDC/RDC, Formal Verification, LEC, synthesis, and timing validation * Collaborate with system, analog, verification, and physical design teams to define ...

OSRAM

Senior Staff Digital Design Engineer

Plano, TX · On-site

Drive design quality and signoff through Lint, CDC/RDC, Formal Verification, LEC, synthesis, and timing validation * Collaborate with system, analog, verification, and physical design teams to define ...

Micron

Staff Digital Design Engineer, HBM

Richardson, TX · On-site

$123K/yr

Collaborate with verification, DFT, physical design, and CAD teams to ensure robust design closure and high coverage, including scan/ATPG readiness and functional/formal verification support. Minimum ...

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Formal Verification information

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How much do formal verification jobs pay per hour?

As of Sep 1, 2026, the average hourly pay for formal verification in Dallas, TX is $20.47, according to ZipRecruiter salary data. Most workers in this role earn between $15.24 and $21.63 per hour, depending on experience, location, and employer.

What is a formal verification?

A Formal Verification job involves using mathematical techniques to prove the correctness of hardware or software designs. Engineers in this role apply formal methods, such as model checking and theorem proving, to ensure that a system behaves as intended without relying solely on traditional testing. This process helps detect critical design flaws early, improving reliability and reducing costly errors. Formal verification is widely used in safety-critical industries like aerospace, automotive, and semiconductor design.

What does a formal verification engineer do?

A Formal Verification engineer's daily responsibilities usually include developing and applying formal models to hardware or software designs, writing assertions, and using verification tools to prove or disprove correctness properties. Collaboration with design, simulation, and verification teams is common to clarify specifications and address any verification gaps. Engineers frequently analyze failures or counterexamples, document findings, and suggest design improvements. This role often involves balancing multiple projects, staying aligned with tight development schedules, and ensuring the highest possible design quality before production.

What skills and qualifications are needed for formal verification?

To thrive in Formal Verification, you need a strong background in computer science, mathematics, and logical reasoning, often supported by a relevant degree in engineering or computer science. Familiarity with formal verification tools such as ModelSim, JasperGold, SystemVerilog Assertions, and proficiency in hardware description languages like Verilog or VHDL are important, and industry certifications can be a plus. Excellent analytical thinking, attention to detail, and strong communication skills help in interpreting specifications and collaborating with cross-functional teams. These skills are crucial to rigorously ensuring hardware or software designs function correctly and meet industry safety and correctness standards.

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Formal Verification jobs near you
Infographic showing various Formal Verification job openings in Dallas, TX as of August 2026, with employment types broken down into 1% As Needed, 81% Full Time, 14% Part Time, 3% Contract, and 1% Nights. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $42,587 per year, or $20.5 per hour.

Design Verification Engineer

Purple Hires Inc

Plano, TX • On-site

$130K - $158K/yr

Contractor

Re-posted 10 days ago

Job description

Job Description and other details –

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Qualifications 

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.

3+ years of experience in ASIC/SoC verification.

Solid understanding of SystemVerilog, digital logic, and hardware verification flows.

Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.

Experience with test planning, testbench development, constrained-random testing, and coverage analysis.

Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Responsibilities 

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.

Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.

Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.

Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.

Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.

Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.

Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.

Participate in design reviews and microarchitecture discussions.