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Associate Asic Verification Engineer Jobs in Dallas, TX

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ...

Purple Hires Inc

ASIC Engineer - Remote

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.

Purple Hires Inc

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

and other details - We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...

IC Enable

AMS Verification Engineer

Richardson, TX · On-site +1

$122K/yr

IC Enable is seeking an experienced AMS Verification Engineer to support advanced analog/mixed ... We specialize in advanced technology development, full-custom ASIC/SoC design, and electronics ...

IC Enable

RTL Design/AMS Verification Engineer

Richardson, TX · On-site +1

$122K - $149K/yr

We specialize in advanced technology development, full-custom ASIC/SoC design, and electronics ... We are seeking an experienced RTL Design / AMS Verification Engineer to support digital and mixed ...

Raytheon Technologies

Principal FPGA Engineer

Mckinney, TX · On-site

$129K - $157K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Raytheon

Principal FPGA Engineer

Mckinney, TX

$129K - $157K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Raytheon

FPGA Engineer II

Plano, TX

$124K - $159K/yr

In this role as an FPGA Engineer II , you will be supporting a development program within the ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

Raytheon Technologies

FPGA Engineer II

Plano, TX · On-site

$117K - $162K/yr

In this role as an FPGA Engineer II , you will be supporting a development program within the ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

RTX

FPGA Engineer II with Security Clearance

Plano, TX · On-site

$118K - $163K/yr

In this role as an FPGA Engineer II , you will be supporting a development program within the ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

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Showing results 1-20

All JobsAssociate Asic Verification Engineer JobsAssociate Asic Verification Engineer Jobs in Dallas, TX

Associate Asic Verification Engineer information

See Dallas, TX salary details

$104.4K

$147.5K

$165.2K

How much do associate asic verification engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for associate asic verification engineer in Dallas, TX is $147,544.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,500.00 and $164,200.00 per year, depending on experience, location, and employer.

What is the difference between Associate Asic Verification Engineer vs Digital Design Engineer?

AspectAssociate Asic Verification EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of verification toolsBachelor's or higher in Electrical Engineering or Computer Engineering; focus on digital circuit design
Work EnvironmentVerification teams within semiconductor or tech companies, using simulation and verification toolsDesign teams creating digital circuits, using HDL languages like VHDL or Verilog
Employer & Industry UsageCommon in semiconductor, electronics, and tech companiesPrevalent in semiconductor, consumer electronics, and hardware development firms

The Associate Asic Verification Engineer primarily focuses on verifying ASIC designs through simulation and testing, ensuring functionality and performance. In contrast, the Digital Design Engineer is responsible for designing digital circuits and implementing hardware logic. Both roles require a strong background in digital electronics, but verification emphasizes testing and validation, while design emphasizes creation and implementation of digital systems.

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Associate Asic Verification Engineer jobs near you
Infographic showing various Associate Asic Verification Engineer job openings in Dallas, TX as of August 2026, with employment types broken down into 1% As Needed, 70% Full Time, 26% Part Time, 1% Temporary, and 2% Contract. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $147,544 per year, or $70.9 per hour.

ASIC DFT Engineer

Purple Hires Inc

Plano, TX • Remote

Contractor

Re-posted 24 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
Year of Exp: 8+ yrs to 15 yrs.
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.