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Asic Engineer Jobs in Dallas, TX (NOW HIRING)

Purple Hires Inc

ASIC Engineer - Remote

Plano, TX · Remote

... ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan ...

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan ...

Raytheon

Senior ASIC/FPGA Design Engineer

Mckinney, TX

$114K - $157K/yr

Typically requires a Bachelor of Science degree in a STEM field (Science, Technology, Engineering, Mathematics). * 5+ years experience in FPGA/ASIC design, RTL development, and verification

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ...

Raytheon

Principal FPGA Engineer

Mckinney, TX

$129K - $157K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

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All JobsAsic Engineer JobsAsic Engineer Jobs in Dallas, TX

Asic Engineer information

See Dallas, TX salary details

$81.6K

$156.5K

$165.7K

How much do asic engineer jobs pay per year?

As of Aug 12, 2026, the average yearly pay for asic engineer in Dallas, TX is $156,541.00, according to ZipRecruiter salary data. Most workers in this role earn between $164,200.00 and $164,200.00 per year, depending on experience, location, and employer.

What does an ASIC engineer do?

An ASIC engineer designs, develops, and tests application-specific integrated circuits used in electronic devices. They work with hardware description languages like VHDL or Verilog, perform simulations, and collaborate with cross-functional teams to optimize chip performance and power consumption. Strong knowledge of digital logic, circuit design, and verification tools is essential for this role.

Are ASIC engineers in demand?

ASIC engineers are in high demand due to the growing need for custom integrated circuits in industries like telecommunications, consumer electronics, and automotive. Their expertise in hardware design, verification, and FPGA tools makes them valuable in developing efficient, specialized chips, with job growth expected to remain strong as technology advances.

What is an ASIC engineer?

An ASIC Engineer works with the design and verification of an Application-Specific Integrated Circuit (ASIC). This type of integrated circuit is designed for a specified purpose, like digital voice recording or cryptocurrency mining. An ASIC engineer has experience and skills that they use to program the integrated circuit based on defined requirements. They are capable of designing and producing ASICs that have over 100 million logic gates.

What are some typical challenges faced by ASIC engineers during the design and verification process?

ASIC Engineers often face challenges such as meeting tight performance, power, and area constraints while ensuring design correctness. Debugging complex issues during simulation and post-silicon validation can be time-consuming and require strong problem-solving skills. Additionally, coordinating with cross-functional teams—such as software, hardware, and verification engineers—is crucial to resolve integration issues and keep projects on schedule. Staying updated with evolving EDA tools and industry standards is also important for success in this role.

How much does an ASIC engineer make?

An ASIC engineer's salary typically ranges from $80,000 to $150,000 annually, depending on experience, location, and industry. Senior roles or those with specialized skills in hardware description languages and verification tools can earn higher compensation.

What is the difference between Asic Engineer vs FPGA Engineer?

AspectAsic EngineerFPGA Engineer
CredentialsBachelor's or Master's in Electrical Engineering, VLSI Design, or related fields; certifications like IEEE or VLSI certificationsBachelor's or Master's in Electrical Engineering, Digital Design, or related fields; similar certifications
Work EnvironmentDesigning and developing custom integrated circuits in labs or design centersImplementing and testing FPGA designs in labs or development environments
Industry UsageUsed in semiconductor companies, electronics manufacturers, and high-performance computingCommon in prototyping, testing, and flexible hardware solutions across industries

While both roles involve digital design and hardware development, Asic Engineers focus on creating custom chips for mass production, whereas FPGA Engineers work on programmable hardware for testing and rapid prototyping. The skills and certifications overlap, but their work environments and end goals differ significantly.

What are the key skills and qualifications needed to thrive as an ASIC engineer, and why are they important?

To thrive as an ASIC Engineer, you need a solid background in digital design, hardware description languages (HDLs) like Verilog or VHDL, and a relevant degree in electrical engineering or a related field. Familiarity with electronic design automation (EDA) tools, simulation software, and knowledge of the ASIC design flow are typically required, with certifications in hardware design being advantageous. Strong problem-solving abilities, attention to detail, and effective communication skills help set top performers apart. These skills are essential for delivering reliable, efficient chip designs while collaborating with cross-functional teams and meeting project specifications.
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What are popular job titles related to Asic Engineer jobs in Dallas, TX? For Asic Engineer jobs in Dallas, TX, the most frequently searched job titles are:
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What cities near Dallas, TX are hiring for Asic Engineer jobs? Cities near Dallas, TX with the most Asic Engineer job openings:
Asic Engineer jobs near you
Infographic showing various Asic Engineer job openings in Dallas, TX as of August 2026, with employment types broken down into 92% Full Time, 3% Part Time, and 5% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $156,541 per year, or $75.3 per hour.

ASIC Engineer - Remote

Purple Hires Inc

Plano, TX • Remote

Contractor

Posted 15 days ago

Job description

Job Description
Key skills for Lead ASIC DFT:
 
please see these key words of in the project description for the profile consideration.
  “SCAN, ATPG, MBIST, Timing Simulations,  SDF, SDC ,  PSV, Diagnosys ,  Pattern Retargeting , Pattern porting,  DRCs,  TetraMax, DFTMax “
Experience
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.