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Cpu Rtl Design Engineer Jobs in Dallas, TX (NOW HIRING)

Glow Networks

RTL Design Engineer

Dallas, TX · On-site

RTL Design Engineer Location: Santa Clara, CA/Remote Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural ...

IC Enable

RTL Design/AMS Verification Engineer

Richardson, TX · On-site +1

$122K - $149K/yr

RTL Design/AMS Verification Engineer Join IC Enable and Help Shape the Future of Semiconductor Innovation For more than 20 years, IC Enable has delivered world-class design IP, semiconductor products ...

Globalfoundries

Staff Engineer AI/ML

Richardson, TX

$106K - $205K/yr

We are seeking an experienced CPU IP Design Engineer. Responsible for Defining, leading and owning RTL development of our latest AI-enabled RISC-V CPU core. The candidate will be responsible for all ...

Texas Instruments

Digital IC Design Engineer

Dallas, TX · On-site

$123K/yr

As a Digital Design Engineer, you will work across the full digital design cycle - from architecture definition and RTL design through functional verification, synthesis, timing closure, and silicon ...

Texas Instruments

Digital IC Design Engineer

Dallas, TX

$123K/yr

As a Digital Design Engineer, you will work across the full digital design cycle - from architecture definition and RTL design through functional verification, synthesis, timing closure, and silicon ...

Cornelis Networks

Senior ASIC Design Engineer

Dallas, TX · On-site +1

... CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI ... Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing ...

Cornelis Networks

Senior ASIC Design Engineer

Dallas, TX · On-site

... CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI ... Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing ...

Micron Technology

HBM Sr RTL Engineer

Richardson, TX · On-site

As an SoC Design Engineer , you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...

Glow Networks

RTL Engineer

Dallas, TX · On-site

The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with ...

Micron

HBM Sr RTL Engineer

Richardson, TX

As an SoC Design Engineer , you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...

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All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Dallas, TX

Cpu Rtl Design Engineer information

See Dallas, TX salary details

$40.1K

$87.2K

$156.8K

How much do cpu rtl design engineer jobs pay per year?

As of Jul 10, 2026, the average yearly pay for cpu rtl design engineer in Dallas, TX is $87,200.00, according to ZipRecruiter salary data. Most workers in this role earn between $67,300.00 and $97,400.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
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Cpu Rtl Design Engineer jobs near you
RTL Design Engineer

RTL Design Engineer

Glow Networks

Dallas, TX • On-site

Full-time

Re-posted 28 days ago

Job description

RTL Design Engineer
Location: Santa Clara, CA/Remote
Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog
Experience in developing micro architectural document from requirements specifications
Experience developing designs from scratch
Experience applying linting and other (QC) quality checking and basic verification of designs.
Experience supporting SoC designers in integration as needed
Strong communication and collaboration skills
Preferred:
-Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces.
- Candidate with design automation, scripting experience (Python) is preferrable
• Develop HW architecture from specification documents.
• Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low power design (UPF/CPF).
• Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
• Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
• Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
• Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
• Take ownership of tasks and drive tasks to closure.

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