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Design Verification Engineer Jobs in Dallas, TX (NOW HIRING)

Purple Hires Inc

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

and other details - We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...

Glow Networks

SOC Design Verification Engineer

Dallas, TX · On-site

$127K - $156K/yr

SOC Design Verification Engineer Location: Redmond, WA (Onsite) Duration: 10 Months Minimum Qualifications • Track record of 'first-pass success' in ASIC development cycles. • Bachelor's degree ...

Analog Devices

Senior Design Verification Engineer

Dallas, TX · On-site

$134K - $164K/yr

Senior Design Verification Engineer About the Role As a Senior Design Verification Engineer at Analog Devices, you will lead verification planning and execution for complex digital and mixed-signal ...

Talent 101, Inc.

Sr. Design Verification Engineer

Dallas, TX · On-site

$134K - $164K/yr

About the role We are looking to add a Sr. Design Verification Engineer to our team in Dallas, TX. What you'll do * Read and understand IP specification * Write and edit C testcases to run on mature ...

IC Enable

RTL Design/AMS Verification Engineer

Richardson, TX · On-site +1

$122K - $149K/yr

RTL Design/AMS Verification Engineer Join IC Enable and Help Shape the Future of Semiconductor Innovation For more than 20 years, IC Enable has delivered world-class design IP, semiconductor products ...

Micron

SMTS Design Verification Engineer

Richardson, TX · On-site

$123K - $150K/yr

As the Design Verification Engineer, you will own pre-silicon functional verification for a high-speed interface chip program. Working on a small, senior team spanning analog design, layout, silicon ...

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All JobsDesign Verification Engineer JobsDesign Verification Engineer Jobs in Dallas, TX

Design Verification Engineer information

See Dallas, TX salary details

$97.4K

$137.7K

$154.1K

How much do design verification engineer jobs pay per year?

As of Jul 28, 2026, the average yearly pay for design verification engineer in Dallas, TX is $137,664.00, according to ZipRecruiter salary data. Most workers in this role earn between $125,500.00 and $153,200.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Design Verification Engineer position, and why are they important?

Design Verification Engineers require a solid background in digital design concepts, computer engineering, and electrical engineering, usually supported by a relevant bachelor’s or master’s degree. Expertise with hardware description languages like Verilog or VHDL, simulation tools, and familiarity with Unix/Linux environments are typical technical requirements, with certifications in FPGA/ASIC design considered advantageous. Strong analytical thinking, problem-solving skills, teamwork, and effective communication help these engineers collaborate closely with design, validation, and development teams. These competencies are vital to ensuring design correctness, catching flaws early, and driving efficient, reliable hardware development.

What is a Design Verification Engineer job?

A Design Verification Engineer ensures that hardware designs function correctly by developing and executing test plans, writing verification code (often in SystemVerilog with UVM), and debugging design issues. They work closely with design and validation teams to confirm specifications are met before manufacturing. Their role is critical in preventing costly design flaws and ensuring high-quality semiconductor products.

What are the most common challenges faced by Design Verification Engineers in their daily work?

Design Verification Engineers often face the challenge of thoroughly validating complex digital designs within tight project deadlines. Debugging intricate issues, dealing with evolving specifications, and ensuring complete coverage during simulation can require a great deal of attention to detail and persistence. Collaboration with designers, validation teams, and often cross-functional groups is critical to resolving ambiguities and preventing errors from reaching production. Adapting to new verification methodologies or tools is also common as technologies and standards advance. These challenges offer valuable learning opportunities and play a crucial role in producing robust, high-quality hardware products.

What are the most commonly searched types of Design Verification Engineer jobs in Dallas, TX? The most popular types of Design Verification Engineer jobs in Dallas, TX are:
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Design Verification Engineer jobs near you
Infographic showing various Design Verification Engineer job openings in Dallas, TX as of June 2026, with employment types broken down into 67% Full Time, and 33% Contract. Highlights an 100% In-person job distribution, with an average salary of $137,664 per year, or $66.2 per hour.

Design Verification Engineer

Purple Hires Inc

Plano, TX • On-site

$130K - $158K/yr

Contractor

Posted 5 days ago

Job description

Job Description and other details –

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Qualifications 

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.

3+ years of experience in ASIC/SoC verification.

Solid understanding of SystemVerilog, digital logic, and hardware verification flows.

Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.

Experience with test planning, testbench development, constrained-random testing, and coverage analysis.

Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Responsibilities 

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.

Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.

Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.

Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.

Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.

Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.

Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.

Participate in design reviews and microarchitecture discussions.