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Formal Verification Jobs (NOW HIRING)

Etched

Formal Verification - DV

San Jose, CA · On-site

$2.0K/mo

You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU ...

DensityAI

DV Formal Verification

Mountain View, CA · On-site

$160K/yr

About the role Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator ...

Apple

Formal Verification Engineer

Austin, TX

$115K - $194K/yr

Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

DensityAI

DV Formal Verification

Mountain View, CA

$200K - $320K/yr

About the role Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator ...

Voltai

Formal Verification Engineer

Palo Alto, CA · On-site

$159K/yr

About this Role In this role, you'll build formal proofs of design correctness using model checking, property verification, and equivalence analysis. You'll collaborate closely with RTL, verification ...

Voltai, Inc

Formal Verification Engineer

Palo Alto, CA · On-site

$159K/yr

About this Role In this role, you'll build formal proofs of design correctness using model checking, property verification, and equivalence analysis. You'll collaborate closely with RTL, verification ...

Swift Hire LLC

Formal ASIC verification

Austin, TX · On-site

Job Title - Formal ASIC verification Location - Austin, Texas Metropolitan Area (Hybrid) Duration - 6+ months Visa - USC and GC Interview - Virtual Basic Qualifications - Bachelor's degree in ...

Qualcomm

CPU Formal Verification Engineer

Santa Clara, CA · On-site

$159K/yr

Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. * Roles and Responsibilities: * Work with design team to understand design intent and bring up ...

Apple

GPU Formal Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification applying formal and property checking methods. This includes deep understanding of the micro-architectural ...

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How much do formal verification jobs pay per hour?

As of Sep 2, 2026, the average hourly pay for formal verification in the United States is $20.70, according to ZipRecruiter salary data. Most workers in this role earn between $15.38 and $21.88 per hour, depending on experience, location, and employer.

What is a formal verification?

A Formal Verification job involves using mathematical techniques to prove the correctness of hardware or software designs. Engineers in this role apply formal methods, such as model checking and theorem proving, to ensure that a system behaves as intended without relying solely on traditional testing. This process helps detect critical design flaws early, improving reliability and reducing costly errors. Formal verification is widely used in safety-critical industries like aerospace, automotive, and semiconductor design.

What does a formal verification engineer do?

A Formal Verification engineer's daily responsibilities usually include developing and applying formal models to hardware or software designs, writing assertions, and using verification tools to prove or disprove correctness properties. Collaboration with design, simulation, and verification teams is common to clarify specifications and address any verification gaps. Engineers frequently analyze failures or counterexamples, document findings, and suggest design improvements. This role often involves balancing multiple projects, staying aligned with tight development schedules, and ensuring the highest possible design quality before production.

What skills and qualifications are needed for formal verification?

To thrive in Formal Verification, you need a strong background in computer science, mathematics, and logical reasoning, often supported by a relevant degree in engineering or computer science. Familiarity with formal verification tools such as ModelSim, JasperGold, SystemVerilog Assertions, and proficiency in hardware description languages like Verilog or VHDL are important, and industry certifications can be a plus. Excellent analytical thinking, attention to detail, and strong communication skills help in interpreting specifications and collaborating with cross-functional teams. These skills are crucial to rigorously ensuring hardware or software designs function correctly and meet industry safety and correctness standards.

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Formal Verification jobs near you
Infographic showing various Formal Verification job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 80% Full Time, 15% Part Time, 3% Contract, and 1% Nights. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $43,051 per year, or $20.7 per hour.

Formal Verification - DV

Etched

San Jose, CA • On-site

$2.0K/mo

Full-time

Medical, Dental, Vision

Re-posted 24 days ago

Job description

About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a Formal Verification Engineer to join our ASIC Design Verification team. You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers. You will work closely with architects, RTL designers, DV engineers, emulation teams, and software/firmware teams to prove design correctness, expose deep corner-case bugs, and improve verification closure across the full chip.
Key Responsibilities
  • Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
  • Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
  • Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
  • Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.
  • Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria.
  • Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up.
  • Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis.
  • Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices.

You May Be a Good Fit If You Have
  • 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon.
  • Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
  • Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
  • Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
  • Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.
  • Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports.
  • Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams.
  • You thrive in a fast-paced startup environment and can take ownership of ambiguous, high-impact verification problems.

Strong Candidates May Also Have Experience With
  • Formal verification of systolic arrays, DMA engines, NoCs, memory subsystems, arithmetic datapaths, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers.
  • Protocol compliance checking, connectivity checking, register verification, datapath validation, reset verification, or deadlock/livelock analysis.
  • Vendor IP integration, encrypted or black-box IP verification, VIP configuration, and contract-based verification around subsystem boundaries.
  • Sequential LEC, floating-point or integer arithmetic proofs, cache coherency checks, interrupt handling, or memory-mapped IO verification.
  • Scripting in Python, TCL, Perl, or similar for automation, regression management, debug, and dashboarding.

Benefits
  • Medical, dental, and vision packages with generous premium coverage
    • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office

How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

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