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Freelance Design Verification Engineer Jobs (NOW HIRING)

Correct Designs

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Design Verification Engineer ID: 1063 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1058 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Arrow Electronics

Design Verification Engineer

Denver, CO · On-site

$167K - $184K/yr

Design Verification Engineer Develop strategies for verification by understanding design architecture and design specifications. Capture all requirements/features of design to create functional ...

Broadcom, Inc.

Design Verification Engineer

San Jose, CA · On-site

$143K - $230K/yr

Lead ASIC Design Verification Engineer We are seeking a highly experienced and visionary Lead/Principal ASIC Design Verification Engineer to drive the verification strategy for our next-generation ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

Broadcom

Design Verification Engineer

San Jose, CA · On-site

$143K - $230K/yr

Lead ASIC Design Verification Engineer We are seeking a highly experienced and visionary Lead/Principal ASIC Design Verification Engineer to drive the verification strategy for our next-generation ...

Lorven Technologies

Design verification Engineer

San Jose, CA · On-site

$158K - $192K/yr

Design Verification Engineer Location: San Jose, CA We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Redolent, Inc.

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ideal candidate will be responsible for verifying complex digital designs using advanced verification ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

iFlow Inc

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

Design Verification Engineer Location:Santa Clara CA Duration: Long term Experience:8-15 Years Description : Key Responsibilities: Strong understanding of SV and UVM and good debugging skills.

Intel

Design Verification Engineer

Santa Clara, CA · On-site

$141K - $200K/yr

Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across ...

Correct Designs

Senior Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Senior Design Verification Engineer ID: 1061 Location: Austin, TX More about this job > Description Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a ...

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Freelance Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do freelance design verification engineer jobs pay per year?

As of Jul 9, 2026, the average yearly pay for freelance design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is the difference between Freelance Design Verification Engineer vs Freelance Hardware Test Engineer?

AspectFreelance Design Verification Engineer

Freelance Design Verification Engineers focus on verifying that hardware designs meet specifications through simulation and testing, often working on FPGA, ASIC, or semiconductor projects. They typically hold certifications in digital design and verification tools, and work in industries like semiconductor, electronics, and tech startups. Freelance Hardware Test Engineers, on the other hand, primarily perform physical testing of hardware prototypes and products, focusing on functional and reliability testing in manufacturing environments. While both roles require technical expertise, verification engineers emphasize simulation and design validation, whereas test engineers focus on real-world hardware testing.

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Freelance Design Verification Engineer jobs near you
Infographic showing various Freelance Design Verification Engineer job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.
Design Verification Engineer

Design Verification Engineer

Correct Designs

Austin, TX

$134K - $164K/yr

Other

Medical, Retirement

Re-posted 25 days ago

Job description

Current Openings >> Design Verification Engineer
Design Verification Engineer
Summary
Title: Design Verification Engineer ID: 1063 Location: Austin, TX
More about this job >
Description

Design Verification Engineer

Looking for new challenges?  Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you.

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates for this role will support verification of advanced CPU/GPU based SOCs.  

Correct Designs is NOT the typical contracting, staff augmentation firm.  Our engineers have respected long term roles with generous hourly rates in excellent team environments.  A typical contract may last 3 years, although we have shorter and even longer term work available. We are well respected in the Design Verification community with clients always seeking new CDI engineers. If you need a few months off between contracts you can take that break and know there will be plenty of work available when you return.  If you like the stability of always working, simply move to the next contract with little time off. Correct Designs does provide health care and retirement plan benefits.

We are based in Austin, Texas with clients throughout the US.  There are opportunities for both in-person and remote work. 
Whether you are an experienced veteran looking for new challenges, or a talented engineer seeking to broaden your experience, we can offer exciting options for your career.  
Correct Designs uses E-Verify to confirm work status eligibility.
 

RESPONSIBILITIES:

  • Verify complex design blocks using equally complex SV/UVM verification environments
  • Develop and execute pre-silicon verification test plans
  • Develop directed and random verification tests to validate block and IP functionality
  • Develop verification components and tools
  • Develop verification functional coverage using industry standard coverage analysis tools/methods
  • Debug regression fails 
  • Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

 REQUIRED SKILLS AND EXPERIENCE:

  • 3 or more years of proven verification experience in a hardware development setting
  • Strong background in SystemVerilog and UVM verification methodologies
  • Strong debug skills and experience with debug tools such as DVE/Verdi
  • Proficiency in Object Oriented programming, computer architecture and data structures
  • Strong analytical/problem solving skills and pronounced attention to details
  • Strong interpersonal and communication skills
  • Must be comfortable working across geographies

DESIRED SKILLS:

  • Experience architecting/developing verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
  • Experience in other related domains such as formal verification, RTL design, or software development

 EDUCATION:

Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science

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