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64 Google Design Verification Engineer Jobs Hiring Near You

ASIC Design Verification Engineer, TPU

Sunnyvale, CA · On-site

$159K - $194K/yr

As an ASIC Design Verification Engineer, you will use design and verification expertise to verify ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...

Silicon Design Verification Engineer

Mountain View, CA · On-site

$160K - $195K/yr

Google's mission is to organize the world's information and make it universally accessible and ... Plan the verification of digital design blocks by analyzing specifications and collaborating with ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1058 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1063 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team. Your role will involve close collaboration with our digital design experts ...

Design Verification Engineer

Austin, TX · Hybrid

$134K - $164K/yr

Design Verification Engineer #368877 Duration: 12+ months (Possible Extension-Long Term Project) Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite) Description * As a Design Verification ...

Design Verification Engineer

Denver, CO · On-site

$167K - $184K/yr

Design Verification Engineer Develop strategies for verification by understanding design architecture and design specifications. Capture all requirements/features of design to create functional ...

Design Verification Engineer The Design Verification Engineer will work on a device in a plug fashion to prove certain properties and connectivity at different levels to validate that the design is ...

Design Verification Engineer

Palo Alto, CA

$159K - $195K/yr

... Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL ... As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams ...

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Infographic showing various Design Verification Engineer job openings at Google in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 100% Physical job distribution.

ASIC Design Verification Engineer, Google Cloud

Google

Sunnyvale, CA • On-site

$159K - $194K/yr

Full-time

Posted 9 days ago


Google rating

8.8

Company rating: 8.8 out of 10

Based on 92 frontline employees who took The Breakroom Quiz

31st of 186 rated software companies


Job description

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 1 year of experience in design verification.
  • Experience with SystemVerilog/Verilog.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with Universal Verification Methodology (UVM) testbenches and methodologies.
  • Experience developing and executing test plans.
  • Familiarity with coverage analysis tools (e.g., Verdi, Questa).
  • Proficiency in SystemVerilog, including object-oriented programming, SystemVerilog Assertions (SVAs) and functional coverage.
  • Excellent problem-solving and debugging skills.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an Application-Specific Integrated Circuit (ASIC) Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $116000 - $166000 (USD) 15% bonus target bonus equity benefits
Learn more about benefits at Google .
Responsibilities
  • Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
  • Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

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