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61 Google Design Verification Engineer Jobs Hiring Near You

Design verification Engineer

San Jose, CA · On-site

$158K - $192K/yr

Design Verification Engineer Location: San Jose, CA We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Design Verification Engineer

Palo Alto, CA · On-site

$159K - $195K/yr

... Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL ... As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

Design Verification Engineer

Palo Alto, CA · On-site

$159K - $195K/yr

... Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL ... As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams ...

Design Verification Engineer

Santa Clara, CA

$160K - $196K/yr

We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve client's abilities ...

Showing results 21-40

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What other companies are hiring for Design Verification Engineer jobs?
Infographic showing various Design Verification Engineer job openings at Google in the United States as of July 2026, with employment types broken down into 100% Full Time. Highlights an 100% Physical job distribution.
Design verification Engineer

Design verification Engineer

Lorven Technologies

San Jose, CA • On-site

$158K - $192K/yr

Full-time

Posted 15 days ago


Job description

Job Title: Design Verification Engineer
Location: San Jose, CA
Job Description:
We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.
Key Responsibilities:
  • Develop and maintain UVM-based verification environments
  • Create test plans, testcases, and coverage models
  • Perform functional verification of RTL designs
  • Debug RTL and testbench issues
  • Drive coverage closure (functional + code)

Required Skills:
  • Strong hands-on with SystemVerilog and UVM
  • Experience in block-level verification
  • Good understanding of digital design fundamentals
  • Experience with debug tools (Verdi, DVE, etc.)

Good to Have:
Exposure to low-power verification (UPF)
Experience with AMBA protocols (AXI/AHB/APB)

Lorven technologies logo

About Lorven technologies

Sourced by ZipRecruiter

Lorven Technologies, headquartered in Plainsboro, New Jersey, United States, is a reputable company in the technology industry, specializing in providing effective IT solutions and consulting services. The company's official website, lorventech.com, offers comprehensive insights into its offerings which include but are not limited to software development, IT consulting, project management, and business analysis. Since its inception, Lorven Technologies has been committed to ensuring efficiency and reliability in delivering IT services to its global clientele, establishing itself as a trusted name in the industry.

Industry

It services

Company size

51 - 200 Employees

Headquarters location

Plainsboro, NJ, US

Year founded

2001

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