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62 Google Design Verification Engineer Jobs Hiring Near You

HCP ONE LLC

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex ...

Ursus, Inc.

Design Verification Engineer

Sunnyvale, CA · Hybrid

$73 - $83/hr

Design Verification Engineer LOCATION: Sunnyvale, CA (Hybrid; 3 days in office/week) DURATION: 6 months with possible extension PAY RANGE: $73 - $83/hr. TOP 3 SKILLS: * SystemVerilog / UVM testbench ...

Ursus

Design Verification Engineer

Sunnyvale, CA · Hybrid

$73 - $83/hr

Design Verification Engineer LOCATION: Sunnyvale, CA (Hybrid; 3 days in office/week) DURATION: 6 months with possible extension PAY RANGE: $73 - $83/hr. TOP 3 SKILLS: * SystemVerilog / UVM testbench ...

Voltai

Design Verification Engineer

Palo Alto, CA

$159K - $195K/yr

... Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL ... As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams ...

Voltai

Design Verification Engineer

Palo Alto, CA · On-site

$150 - $210/hr

... Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL ... As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams ...

Voltai

Design Verification Engineer

Palo Alto, CA · On-site

$159K - $195K/yr

... Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL ... As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams ...

Lorven Technologies

Design verification Engineer

San Jose, CA · On-site

$158K - $192K/yr

Design Verification Engineer Location: San Jose, CA We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

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Design Verification Engineer

HCP ONE LLC

San Jose, CA • On-site

$159K - $194K/yr

Other

Posted 24 days ago

Job description

Job Title: Design Verification Engineer
Location: San Jose, CA
Experience: 8+ Years
Type: Contract
Description:
This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle.
 
Key Skills Required
·  8+ years of Design Verification experience in semiconductor/ASIC/SoC development.
·  Strong expertise in System Verilog.
·  Extensive experience with UVM (Universal Verification Methodology).
·  Experience verifying IP blocks and SoC-level designs.
·  Strong debugging and functional verification skills.
·  Scripting experience in Python, Perl, or Shell.
·  Ability to collaborate with RTL designers and architects to resolve design issues.
Experience writing:
o   Testbenches
o   Testcases
o   Assertions (SVA)
o   Functional coverage
 
Roles & Responsibilities:
·  Develop and maintain UVM-based verification environments.
·  Create verification plans based on design specifications.
·  Write System Verilog testbenches and assertions.
·  Execute simulations and analyze failures.
·  Debug RTL and verification issues.
·  Measure functional coverage and ensure verification closure.
·  Automate regression runs using scripting languages.
·  Work closely with design and architecture teams throughout the development cycle.
 
Must-Have Skills:
·  8+ years Design Verification
·  System Verilog
·  UVM
·  IP/SoC Verification
·  Functional Verification
·  Assertions (SVA)
·  Python/Perl/Shell scripting
·  Debugging RTL issues

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