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62 Google Design Verification Engineer Jobs Hiring Near You

Design Verification Engineer

Sunnyvale, CA

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

Design Verification Engineer

Santa Clara, CA

$160K - $196K/yr

We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve client's abilities ...

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

Design Verification Engineer Location:Santa Clara CA Duration: Long term Experience:8-15 Years Description : Key Responsibilities: Strong understanding of SV and UVM and good debugging skills.

Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across ...

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ideal candidate will be responsible for verifying complex digital designs using advanced verification ...

Showing results 41-60

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Do people get enough training when they start at Google?

Most people got enough training when they started.
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Based on data from 48 people who took the Breakroom Quiz between June 2025 and June 2026.

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What other companies are hiring for Design Verification Engineer jobs?
Infographic showing various Design Verification Engineer job openings at Google in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 100% Physical job distribution.

Design Verification Engineer

Baidu USA

Sunnyvale, CA

$159K - $194K/yr

Other

Posted 18 days ago


Job description

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?

We're looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.

Description

We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment. Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.

You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.

Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage.

Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.

Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.

Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.

Qualifications 

  • Minimum 5 years of experience of UVM based verification on a significantly complex project.
  • Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
  • Advanced knowledge of System Verilog and the UVM methodology.
  • Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
  • Good practice of one scripting language (Perl, Python, Tcl) no preference.
  • SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
  • Familiar with C/C++.
  • Formal Verification (Model Checking, Equivalence Checking).
  • Excellent communication skills in both English and Chinese.

Culture Fit:

  • Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
  • Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
  • Hungry to learn: We are eager to see you learn new skills and grow.
  • Team orientation: We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.

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