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60 Rivos Design Verification Engineer Jobs Hiring Near You

Design Verification Engineer

Sunnyvale, CA · Hybrid

$161K - $197K/yr

Design Verification Engineer Location: Sunnyvale, CA Job Type: Full-time Work Arrangement: Onsite role, Work from Client Office - 5 days a week Interview: Two rounds of Video interview We are seeking ...

Design Verification Engineer

Sunnyvale, CA · Hybrid

$159K - $194K/yr

Design Verification Engineer Location: Sunnyvale, CA Job Type: Full-time Work Arrangement: Onsite role, Work from Client Office - 5 days a week Interview: Two rounds of Video interview We are seeking ...

Design Verification Engineer

Sunnyvale, CA · Hybrid

$161K - $197K/yr

Design Verification Engineer Location: Sunnyvale, CA Job Type: Full-time Work Arrangement: Onsite role, Work from Client Office - 5 days a week Interview: Two rounds of Video interview We are seeking ...

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Design Verification Engineer ID: 1063 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Design Verification Engineer ID: 1058 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Location: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job Summary We are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC ...

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex ...

Design Verification Engineer

Denver, CO · On-site

$167K - $184K/yr

Design Verification Engineer Develop strategies for verification by understanding design architecture and design specifications. Capture all requirements/features of design to create functional ...

Design Verification Engineer LOCATION: Sunnyvale, CA (Hybrid; 3 days in office/week) DURATION: 6 months with possible extension PAY RANGE: $73 - $83/hr. TOP 3 SKILLS: * SystemVerilog / UVM testbench ...

Design Verification Engineer LOCATION: Sunnyvale, CA (Hybrid; 3 days in office/week) DURATION: 6 months with possible extension PAY RANGE: $73 - $83/hr. TOP 3 SKILLS: * SystemVerilog / UVM testbench ...

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Design Verification Engineer

Abode Techzone LLC

Sunnyvale, CA • On-site

$161K - $197K/yr

Full-time

This job post has expired today. Applications are no longer accepted.


Job description

Design Verification Engineer

We are seeking a talented and experienced Design Verification Engineer to join our dynamic team. The ideal candidate will have a strong background in universal verification methodologies and hands-on experience in verifying complex digital designs.

Responsibilities:

  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause, and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality
  • Develop and execute comprehensive verification plans to ensure design quality and functionality.
  • Implement coverage-driven verification strategies to achieve thorough testing of design features.
  • Utilize SystemVerilog (SV) and Universal Verification Methodology (UVM) for creating and executing testbenches.
  • Perform debugging and root-cause analysis to identify issues and ensure timely resolution.
  • Drive design verification closure by ensuring all identified issues are addressed and resolved effectively.

Minimum Qualifications:

  • B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
  • 10+ years of proven experience as a Design Verification Engineer.
  • Hands-on experience in Verilog, System Verilog, C/C++ based verification, and UVM methodology
  • Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies
  • Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.
  • Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle

Preferred Qualifications:

  • Experience in the development of UVM based verification environments from scratch
  • Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
  • Experience with revision control systems like Mercurial(Hg), Git or SVN
  • Experience with verification of ARM/RISC-V based sub-systems or SoCs

Abode TechZone logo

About Abode TechZone

Sourced by ZipRecruiter

Abode is fast-growing staffing corporation, business growth depends on putting the right people in place — the professional talent that sets your organization apart from the competition. Abode’s vision is to provide best ever IT’s Staff Solutions services with an effective strategy which can address market fluctuations in key areas, such as time, cost, risk, flexibility, control, and expertise. We target to connect our partners with the best professional talent you need.

Industry

Recruiting and staffing services

Company size

11 - 50 Employees

Headquarters location

New York, NY, US

Year founded

2019

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