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60 Rivos Design Verification Engineer Jobs Hiring Near You

Intel

Design Verification Engineer

Santa Clara, CA

$141K - $200K/yr

Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across ...

iFlow Inc

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

Design Verification Engineer Location:Santa Clara CA Duration: Long term Experience:8-15 Years Description : Key Responsibilities: Strong understanding of SV and UVM and good debugging skills.

Texas Instruments

Design Verification Engineer

Knoxville, TN · On-site

$129K - $158K/yr

As a Design Verification Engineer, you will work across the full verification cycle - from developing detailed verification plans and building test benches through running coverage regressions ...

US Tech Solutions

Design Verification Engineer

Santa Clara, CA · On-site

$160K - $196K/yr

We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve client's abilities ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

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Design Verification Engineer, Principal

YK Solutions LLC

Santa Clara, CA

$158K - $317K/yr

Full-time

Re-posted 16 days ago

Job description

Design Verification Engineer, PrincipalDesign Verification Engineer, PrincipalPosition Title

Design Verification Engineer, Principal

Location: Santa Clara, CA

Work Type: Onsite

Employment Type: Permanent

Category: Engineering / Architecture

Compensation
  • Salary: $158,600 - $317,800 per year
Benefits

Benefits information not specified in job description.

Company Overview

(Confidential Client) is a leading company that designs cutting-edge chips for the general market and specific customers, including major telecom organizations and automotive companies. The company specializes in facilitating high-speed data transfers through advanced technology.

Position Summary

As a leading member of the Network Switching team and Design Verification Team at (Confidential Client), you will verify all circuitry that goes inside our chips, ensuring each design meets customer specifications. You will develop the architecture for a functional verification environment and may include project management responsibilities, leading a team of verification engineers on a project level.

Must-Haves
  • BS in Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification, firmware, and software development experience (or MS/PhD with 5+ years experience)
  • Proven track record of leading Design Verification implementation activities and tape-out of complex SOCs under tight schedules
  • In-depth understanding and experience with SystemVerilog and UVM
  • In-depth experience writing detailed test plans and building sophisticated, directed, random-verification environments
  • Experience with scripting languages such as Python or Perl and EDA Verification tools
  • Experience with Object-Oriented Design and implementation
  • Good understanding of Linux operating systems
Primary Functions
  • Write verification test plans using random techniques and coverage analysis, working with designers to ensure completeness
  • Develop tests and tune the environment to achieve coverage goals
  • Debug failures and work with designers to resolve issues
  • Verify boot code and architect, develop, and maintain tools to streamline the design of state-of-the-art multi-core SoCs
  • Transform requirements from engineering teams into software tools that are easy to use and scalable within highly parallel compute environments
  • Conduct unit and regression testing of software tools
  • Develop the architecture for functional verification environments, including reference models and bus-functional monitors and drivers
  • Contribute to verification methodology development
Required Skills
  • SystemVerilog and UVM expertise
  • Scripting languages (Python or Perl)
  • EDA Verification tools
  • Object-Oriented Design and implementation
  • Linux operating system knowledge
  • Good programming skills, especially C++ and ARM assembly (desired)
  • Understanding of networking protocols (a plus)
  • Diligent and detail-oriented
  • Ability to take initiative and handle assignments with minimal supervision
  • Ability to accept and work with differing opinions
  • Open-minded approach to problem-solving
  • Ability to learn on the fly and work in a fast-paced environment