Digital Verification Engineer Jobs (NOW HIRING)

Digital Verification Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type: Long-term contract Duration: 12 months Minimum Qualifications * The ideal candidate should have a BS ...

Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0-10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable ...

Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0-10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable ...

Computer Architecture, Digital Integrated Circuit Design, Microprocessor system design; Verilog and System Verilog; UVM and Formal verification; Programming language: Python or C/C++, Cache; and AHB ...

Computer Architecture, Digital Integrated Circuit Design, Microprocessor system design; Verilog and System Verilog; UVM and Formal verification; Programming language: Python or C/C++, Cache; and AHB ...

Computer Architecture, Digital Integrated Circuit Design, Microprocessor system design; Verilog and System Verilog; UVM and Formal verification; Programming language: Python or C/C++, Cache; and AHB ...

What will you do at Ciena as a Digital Verification Engineer? The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to ...

... Digital Circuit and Logic Design; 4. UVM Verification and Formal verification; 5. Testbench; 6. Physical Design Flow; 7. Verilog and System Verilog; and 8. Programming language: Python or C/C+

... 2. Digital Integrated Circuit Design, 3. Microprocessor system design; 4. Verilog and System Verilog; 5. Formal verification; 6. Programming language: Python or C/C++, 7. SQL, Jenkins, 8. Data ...

... Digital Circuit and Logic Design; 4. UVM Verification and Formal verification; 5. Testbench; 6. Physical Design Flow; 7. Verilog and System Verilog; and 8. Programming language: Python or C/C+

Digital Verification Engineer Responsibilities: * Develop test plans and verification infrastructure for low-power ASIC designs * Build verification environments using SV/UVM methodology * Build ...

... 2. Digital Integrated Circuit Design, 3. Microprocessor system design; 4. Verilog and System Verilog; 5. Formal verification; 6. Programming language: Python or C/C++, 7. SQL, Jenkins, 8. Data ...

... engineers whose mission is to push the frontiers of what is possible today and define the future. Key qualifications : * Minimum 3 years of experience in digital ASIC verification. * Excellence in ...

... digital world. & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC ...

... digital world. & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC ...

We are looking for you to join our team as a Principal Digital Verification Engineer or Sr. Principal Digital Verification Engineer based out of San Diego, CA. At the Northrop Grumman San Diego ...

We are looking for you to join our team as a Principal Digital Verification Engineer or Sr. Principal Digital Verification Engineer based out of San Diego, CA. At the Northrop Grumman San Diego ...

Senior Digital Verification Engineer We're is looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions.

Senior Digital Verification Engineer Primary Location: Chandler, Arizona, USA Role Summary: The Advanced Power Systems group within NXP's Power and Energy Business Line is seeking a Senior Digital ...

Senior Digital Verification Engineer Primary Location: Chandler, Arizona, USA Role Summary: The Advanced Power Systems group within NXP's Power and Energy Business Line is seeking a Senior Digital ...