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Digital Verification Engineer Jobs (NOW HIRING)

Digital Verification Engineer We are seeking an expert Digital Verification Engineer to propose and implement innovative verification strategies for simulating and validating functional blocks, cores ...

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Description As a Wireless Radio Verification Engineer, you'll verify Radio digital controllers combined with RF subsystems that enable exceptional wireless performance. You'll develop verification ...

PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework. * 5+ years' experience in design plus verification of ASIC or FPGA * Strong knowledge of ASIC development process ...

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Signal Verification Engineer

San Jose, CA · On-site

$159K/yr

Create and maintain AMS (Analog Mixed Signal) and DMS (Digital Mixed Signal) verification ... Bachelor's degree in Electrical/Electronics Engineering or related field. * 2+ years of experience ...

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Digital Verification Engineer information

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$105.5K

$149.2K

$167K

How much do digital verification engineer jobs pay per year?

As of Sep 12, 2026, the average yearly pay for digital verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a digital verification engineer?

A Digital Verification Engineer is responsible for ensuring the correctness of digital designs before manufacturing. They develop and implement testbenches using hardware description languages like SystemVerilog and methodologies like UVM. Their role involves writing test cases, debugging failures, and improving verification efficiency. The goal is to identify design issues early in the development cycle, reducing costly revisions.

What are some common daily responsibilities for a digital verification engineer?

As a Digital Verification Engineer, your daily tasks typically include developing and maintaining testbenches, writing and executing test cases, and analyzing simulation results to identify potential design issues. You’ll work closely with design engineers to review specifications and debug hardware or firmware discrepancies, ensuring that the digital designs meet all functional and timing requirements. Collaborating within cross-functional teams and participating in regular code reviews are also standard parts of the workflow. This hands-on and collaborative environment helps accelerate product development and ensures high-quality deliverables.

What are the key skills and qualifications needed to thrive as a digital verification engineer?

To thrive as a Digital Verification Engineer, you need a solid background in digital design, computer engineering, and experience with verification methodologies, often supported by a Bachelor’s or Master’s degree in a related field. Proficiency with hardware description languages (such as Verilog, VHDL), simulation tools (like ModelSim, Questa), scripting languages (Python, Perl), and familiarity with standard verification methodologies (UVM, SystemVerilog) are typically required. Attention to detail, strong analytical thinking, and effective communication skills are crucial soft skills for collaborating with design teams and troubleshooting complex systems. These abilities ensure accurate verification outcomes, minimize design errors, and facilitate seamless teamwork in fast-paced semiconductor environments.

Are digital verification engineers in demand?

Digital verification engineers are in high demand due to the growth of semiconductor and electronics industries, as well as the increasing complexity of integrated circuits. Skills in hardware description languages like Verilog or VHDL, along with experience in simulation tools, enhance employability in this field.

How do you become a digital verification engineer?

To become a digital verification engineer, typically a bachelor's degree in electrical engineering, computer engineering, or a related field is required. Gaining experience with hardware description languages like Verilog or VHDL, understanding digital design, and proficiency with verification tools such as UVM or SystemVerilog are essential. Certifications or hands-on experience in FPGA or ASIC verification can also enhance job prospects.

How much do digital verification engineers make in the US?

Digital verification engineers in the US typically earn between $80,000 and $130,000 annually, with experienced professionals and those in senior roles earning higher salaries. Compensation varies based on experience, location, and industry, and often includes skills in hardware description languages like Verilog or VHDL and familiarity with verification tools.

What cities are hiring for Digital Verification Engineer jobs?

Cities with the most Digital Verification Engineer job openings:

What are the most commonly searched types of Digital Verification Engineer jobs?

The most popular types of Digital Verification Engineer jobs are:

What states have the most Digital Verification Engineer jobs?

States with the most job openings for Digital Verification Engineer jobs include:

What are popular job titles related to Digital Verification Engineer jobs?

For Digital Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Digital Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 14% Internship, 58% Full Time, 14% Part Time, and 14% Contract. Highlights an 86% In-person, and 14% Hybrid job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Digital Verification Engineer - Weapon Subsystems 2

Albuquerque, NM • On-site

Sandia
Marketing • 11 - 50 employees

$121K - $237K/yr

Full-time

Medical, Retirement, PTO

This job post has expired 1 day ago. Applications are no longer accepted.


Key responsibilities

  • Translate digital design requirements into precise verification checks.

  • Adapt requirements into SystemVerilog Assertions (SVA) for verification.

  • Collaborate with designers and verification specialists to ensure correct system deployment.


Job description

About Sandia
Sandia National Laboratories is the nation's premier science and engineering lab for national security and technology innovation, with teams of specialists focused on cutting-edge work in a broad array of areas. Some of the main reasons we love our jobs:
  • Challenging work with amazing impact that contributes to security, peace, and freedom worldwide
  • Extraordinary co-workers
  • Some of the best tools, equipment, and research facilities in the world
  • Career advancement and enrichment opportunities
  • Flexible work arrangements for many positions include 9/80 (work 80 hours every two weeks, with every other Friday off) and 4/10 (work 4 ten-hour days each week) compressed workweeks, part-time work, and telecommuting (a mix of onsite work and working from home)
  • Generous vacation, strong medical and other benefits, competitive 401k, learning opportunities, relocation assistance and amenities aimed at creating a solid work/life balance*

World-changing technologies. Life-changing careers. Learn more about Sandia at: http://www.sandia.gov
*These benefits vary by job classification.
What Your Job Will Be Like
Sandia National Laboratories is seeking a Digital Verification Engineer (R&D Electrical Engineer) with expertise in formal verification tools to ensure the correct functionality of ASIC and FPGA designs. The ideal candidate will have hands-on experience with VHDL and Verilog design languages and be proficient in using SystemVerilog Assertions (SVA) within formal verification environments.
Success in this role requires a strong foundation in digital design principles, a detail-oriented and logical approach to problem-solving, and excellent written communication skills.
As a Digital Verification Engineer, you will:
  • Translate digital design requirements at various development stages into precise, unambiguous checks against the implementation.
  • Adapt diverse requirements¿including functionality, safety, and information protection¿into SystemVerilog Assertions (SVA) for verification.
  • Evaluate trade-offs in formal analysis complexity to ensure verification tasks remain tractable and efficient.
  • Collaborate closely with designers, system engineers, and other verification specialists to deploy systems that are verifiably correct.
  • Produce clear, concise, and well-documented archival reports detailing verification activities and results.
  • Present verification findings at technical reviews to peers and customers.
  • Continuously learn and apply new formal verification techniques and methodologies.

While this position is ideally based on-site in California or New Mexico with hybrid flexibility, remote work from any U.S. State may be considered. Candidates working remotely must be able to travel to the California site approximately once per month to support mission needs.
Applicants on this requisition may be interviewed by multiple organizations at Sandia National Laboratories.
Salary Range
$121,900 - $237,800
*Salary range is estimated, and actual salary will be determined after consideration of the selected candidate's experience and qualifications, and application of any approved geographic salary differential.
Qualifications We Require
  • A Bachelor's degree in a relevant discipline, or an equivalent combination of directly relevant education and engineering or scientific experience that demonstrates the knowledge, skills, and ability to perform independent research and development.
  • Ability to obtain and maintain a DOE Q-level security clearance.

Qualifications We Desire
The ideal R&D S&E Electrical Engineer candidate for Sandia National Laboratories will in addition possess the following:
  • Graduate degree in Electrical Engineering or a highly related field where an independent research project was a graduation requirement (e.g., independent project, thesis, or dissertation).
  • Ability to work independently and collaborate well in a multidisciplinary team of designers and test engineers.
  • Outstanding verbal and written skills, including the ability to develop and present briefings that are clear and compelling.

Also, for this posting we are seeking individuals with the following experience:
  • Several years of experience applying formal verification techniques to FPGA or ASIC designs.
  • Proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA).
  • Strong analytical skills with meticulous attention to detail in both technical work and documentation.

About Our Team
Department 8421 designs, tests, and deploys advanced electronic systems for various national security applications. The department has a broad mix of skills and technical resources in areas such as digital communications, sensors, radio frequency (RF)/microwave, field-programmable gate array (FPGA) design, power supply technology, general electronics-circuit design, digital signal processing (DSP) algorithms and coding, mechanical design and analysis, and systems engineering.
Posting Duration
This posting will be open for application submissions for a minimum of three (3) calendar days, including the 'posting date'. Sandia reserves the right to extend the posting date at any time.
Security Clearance
Sandia is required by DOE to conduct a pre-employment drug test and background review that includes checks of personal references, credit, law enforcement records, and employment/education verifications. Applicants for employment need to be able to obtain and maintain a DOE Q-level security clearance, which requires U.S. citizenship. If you hold more than one citizenship (i.e., of the U.S. and another country), your ability to obtain a security clearance may be impacted.
Applicants offered employment with Sandia are subject to a federal background investigation to meet the requirements for access to classified information or matter if the duties of the position require a DOE security clearance. Substance abuse or illegal drug use, falsification of information, criminal activity, serious misconduct or other indicators of untrustworthiness can cause a clearance to be denied or terminated by DOE, resulting in the inability to perform the duties assigned and subsequent termination of employment.
EEO
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status and any other protected class under state or federal law.
NNSA Requirements for MedPEDs
If you have a Medical Portable Electronic Device (MedPED), such as a pacemaker, defibrillator, drug-releasing pump, hearing aids, or diagnostic equipment and other equipment for measuring, monitoring, and recording body functions such as heartbeat and brain waves, if employed by Sandia National Laboratories you may be required to comply with NNSA security requirements for MedPEDs.
If you have a MedPED and you are selected for an on-site interview at Sandia National Laboratories, there may be additional steps necessary to ensure compliance with NNSA security requirements prior to the interview date.
Position Information
This Limited Term Employee (LTE) position is a temporary position for one year term, which may be renewed at Sandia's discretion up to a maximum of seven years.
Individuals in LTE positions may bid on regular Sandia positions as internal candidates, and in some cases may be converted to regular career positions during their term if warranted by ongoing operational needs, continuing availability of funds, and satisfactory job performance.