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Senior Digital Verification Engineer Jobs (NOW HIRING)

Ciena

Digital Verification Engineer Expert

New York, NY · On-site

$147.10K - $234.90K/yr

ASIC Engineer (Digital Verification Engineer Expert (P4)) How You Will Contribute: The Wavelogic ... Possibility of reporting directlyto the Senior Manager as an ASIC Verification Prime * As an ASIC ...

Ciena

Digital Verification Engineer Expert

Manhattan, NY

$147.10K - $234.90K/yr

ASIC Engineer (Digital Verification Engineer Expert (P4)) How You Will Contribute: The Wavelogic ... Possibility of reporting directlyto the Senior Manager as an ASIC Verification Prime * As an ASIC ...

Ciena

Digital Verification Engineer - New Grad

Rochester, NY · On-site

$79.30K - $126.70K/yr

What will you do at Ciena as a Digital Verification Engineer? The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to ...

Luxtera

Digital Verification Engineer

Carlsbad, CA · On-site

$141.10K - $172.20K/yr

This position is for PHY transceiver digital blocks level and chip level verification. ESSENTIAL ... Objected Oriented Programming. * Experience with expertise in the chip level verification ...

Draper

UVM Digital Verification Engineer

Cambridge, MA · On-site

$75K - $156K/yr

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

Protingent

Digital Verification CAD Engineer

San Jose, CA · On-site

$90 - $120/hr

Digital Verification CAD Engineer Position Description : Protingent Staffing has an exciting contract Digital Verification CAD Engineer with our client located in San Jose, CA. : * We are seeking a ...

Silabs

Digital Verification Engineer I

Austin, TX · Hybrid

$84K - $156K/yr

Experience with Verilog and SystemVerilogfor digital design and verification through professional setting, internships, coursework, research, or project work. * Programming and scripting experience ...

Draper

UVM Digital Verification Engineer

Cambridge, MA

$75K - $156K/yr

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

Silabs

Staff Digital Verification Engineer

Austin, TX · Hybrid

$150.50K - $279.50K/yr

Staff Digital Verification Engineer Austin, TX Meet the Team We arefocused on producingworld-classWireless MCUproducts. The architecturespecifications, design, verification, emulation, and ...

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Senior Digital Verification Engineer information

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$134.6K

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How much do senior digital verification engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for senior digital verification engineer in the United States is $134,577.00, according to ZipRecruiter salary data. Most workers in this role earn between $107,500.00 and $157,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Senior Digital Verification Engineer, and why are they important?

To thrive as a Senior Digital Verification Engineer, you need expertise in digital design verification methodologies, strong knowledge of hardware description languages (such as Verilog/SystemVerilog), and typically a bachelor's or master's degree in electrical or computer engineering. Proficiency with tools like UVM (Universal Verification Methodology), simulation environments (e.g., Mentor Questa, Synopsys VCS), and scripting languages (Python, Perl, TCL) is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design teams and troubleshoot complex issues. These skills ensure robust verification processes, reducing design errors and enabling the successful delivery of reliable, high-performance digital products.

How does a Senior Digital Verification Engineer typically collaborate with design and software teams during the verification process?

Senior Digital Verification Engineers work closely with both hardware design and software development teams to ensure that digital circuits meet all specifications and function correctly. They often participate in regular cross-functional meetings to align on design intent, clarify requirements, and address any ambiguities early in the development cycle. Effective collaboration involves sharing test plans, debugging issues together, and providing feedback to refine both hardware and firmware. This collaborative approach helps streamline verification cycles and catch issues before they become costly to fix.

What does a Senior Digital Verification Engineer do?

A Senior Digital Verification Engineer is responsible for ensuring the correctness and quality of complex digital integrated circuits or systems before they are manufactured. They develop and implement verification plans, create testbenches, write test cases, and run simulations to catch design flaws early in the development process. These engineers often use hardware description languages like SystemVerilog and verification methodologies such as UVM. Additionally, they collaborate closely with design engineers and other team members to debug issues and improve design reliability.
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Senior Digital Verification Engineer jobs near you
Senior Digital Verification Engineer

Senior Digital Verification Engineer

Ethan Alexander Group

San Francisco, CA • On-site

$180K - $210K/yr

Full-time

Posted 21 days ago

Job description

Senior Digital Verification Engineer


We're is looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities commensurate with experience.


Responsibilities:


  • Continually advance verification flow with emphasis on reusability from project to project.
  • Be a significant individual contributor.
  • Manage and direct other DV engineers.
  • Provide best in class DV at both IP and SOC level.
  • Create and, via peer reviews, vet test plans.
  • Track progress using quantitative metrics.
  • Make go/no go recommendations for tape outs.


Requirements:


  • Proficiency in verification test planning and test bench architecture.
  • Knowledgeable of common DV techniques such as assertions, SV, OVM/UVM, constrained random, and coverage (code/functional/assertion).
  • Strong knowledge of Verilog or VHDL, C.
  • Capable of scripting and leveraging automation. Able to set up and maintain automated regressions.
  • Ability to understand design specifications and map them to a test plan. Ability to implement test plans. Willingness to debug designs and work cooperatively with logic designers.
  • Ability to run and debug gate level simulations.
  • BS or MS (preferred) degree in EE or equivalent, with 10+ years of experience


Nice to Have:


  • DV experience with designs deploying low power techniques, particularly power islands and associated UPF.
  • Experience developing C-based tests for ARM-M processors.
  • Understanding of secure/non-secure spaces and dynamic clock frequency switching.
  • Wireless communications, knowledge of BLE at the protocol level