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Senior Digital Verification Engineer Jobs (NOW HIRING)

NextHop AI

Digital Verification Engineer

Santa Clara, CA

$160K - $196K/yr

Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0-10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable ...

NextHop AI

Digital Verification Engineer

Santa Clara, CA · On-site

$160K - $196K/yr

Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0-10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable ...

Ciena Corporation

NY · On-site

$147.10 - $234.90/hr

To further strengthen our team, we are looking for an expert digital verification engineer to work ... Possibly report directly to the Senior Manager as an ASIC Verification Prime. * As an ASIC ...

New

Neuralink

Digital Verification Engineer

South San Francisco, CA · On-site

$163K - $199K/yr

... engineers whose mission is to push the frontiers of what is possible today and define the future. Key qualifications : * Minimum 3 years of experience in digital ASIC verification. * Excellence in ...

TRC Talent Solutions

Verification Engineer

Suwanee, GA · Hybrid

$126K/yr

Senior Verification Engineer (DDR5 / PMIC / CXL) Johns Creek, GA (Hybrid/Onsite) About the ... digital verification methodologies Solid debugging and problem-solving skills Preferred ...

Draper

UVM Digital Verification Engineer

Cambridge, MA · On-site

$75K - $156K/yr

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

6AM City, LLC

WI · On-site

$140 - $190/hr

Principal Digital Verification Engineer * Verification of DDR5 Data Buffer to meet functional and performance specifications. * Be able to integrate and test on System-level and block level using UVM ...

New

Draper

UVM Digital Verification Engineer

Cambridge, MA · On-site

$75K - $156K/yr

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

Draper

Senior UVM Digital Verification Engineer

Cambridge, MA · On-site

$114K - $156K/yr

Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply ...

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Senior Digital Verification Engineer information

See salary details

$70.5K

$134.6K

$195K

How much do senior digital verification engineer jobs pay per year?

As of Aug 8, 2026, the average yearly pay for senior digital verification engineer in the United States is $134,577.00, according to ZipRecruiter salary data. Most workers in this role earn between $107,500.00 and $157,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a senior digital verification engineer, and why are they important?

To thrive as a Senior Digital Verification Engineer, you need expertise in digital design verification methodologies, strong knowledge of hardware description languages (such as Verilog/SystemVerilog), and typically a bachelor's or master's degree in electrical or computer engineering. Proficiency with tools like UVM (Universal Verification Methodology), simulation environments (e.g., Mentor Questa, Synopsys VCS), and scripting languages (Python, Perl, TCL) is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design teams and troubleshoot complex issues. These skills ensure robust verification processes, reducing design errors and enabling the successful delivery of reliable, high-performance digital products.

How does a senior digital verification engineer typically collaborate with design and software teams during the verification process?

Senior Digital Verification Engineers work closely with both hardware design and software development teams to ensure that digital circuits meet all specifications and function correctly. They often participate in regular cross-functional meetings to align on design intent, clarify requirements, and address any ambiguities early in the development cycle. Effective collaboration involves sharing test plans, debugging issues together, and providing feedback to refine both hardware and firmware. This collaborative approach helps streamline verification cycles and catch issues before they become costly to fix.

What does a senior digital verification engineer do?

A Senior Digital Verification Engineer is responsible for ensuring the correctness and quality of complex digital integrated circuits or systems before they are manufactured. They develop and implement verification plans, create testbenches, write test cases, and run simulations to catch design flaws early in the development process. These engineers often use hardware description languages like SystemVerilog and verification methodologies such as UVM. Additionally, they collaborate closely with design engineers and other team members to debug issues and improve design reliability.
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Senior Digital Verification Engineer jobs near you
Infographic showing various Senior Digital Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 82% Full Time, 13% Part Time, and 5% Contract. Highlights an 88% Physical, 3% Hybrid, and 9% Remote job distribution, with an average salary of $134,577 per year, or $64.7 per hour.

Senior Digital Verification Engineer

Ethan Alexander Group

San Francisco, CA

$180K - $210K/yr

Full-time

Re-posted 4 days ago

Job description

Senior Digital Verification Engineer


We're is looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities commensurate with experience.


Responsibilities:


  • Continually advance verification flow with emphasis on reusability from project to project.
  • Be a significant individual contributor.
  • Manage and direct other DV engineers.
  • Provide best in class DV at both IP and SOC level.
  • Create and, via peer reviews, vet test plans.
  • Track progress using quantitative metrics.
  • Make go/no go recommendations for tape outs.


Requirements:


  • Proficiency in verification test planning and test bench architecture.
  • Knowledgeable of common DV techniques such as assertions, SV, OVM/UVM, constrained random, and coverage (code/functional/assertion).
  • Strong knowledge of Verilog or VHDL, C.
  • Capable of scripting and leveraging automation. Able to set up and maintain automated regressions.
  • Ability to understand design specifications and map them to a test plan. Ability to implement test plans. Willingness to debug designs and work cooperatively with logic designers.
  • Ability to run and debug gate level simulations.
  • BS or MS (preferred) degree in EE or equivalent, with 10+ years of experience


Nice to Have:


  • DV experience with designs deploying low power techniques, particularly power islands and associated UPF.
  • Experience developing C-based tests for ARM-M processors.
  • Understanding of secure/non-secure spaces and dynamic clock frequency switching.
  • Wireless communications, knowledge of BLE at the protocol level