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Weekend Digital Verification Engineer Jobs (NOW HIRING)

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

Experience with Verilog and SystemVerilogfor digital design and verification through professional setting, internships, coursework, research, or project work. * Programming and scripting experience ...

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

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Weekend Digital Verification Engineer information

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$80K

$142.6K

$203.5K

How much do weekend digital verification engineer jobs pay per year?

As of Jun 27, 2026, the average yearly pay for weekend digital verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.
What are the most commonly searched types of Digital Verification Engineer jobs? The most popular types of Digital Verification Engineer jobs are:
Infographic showing various Weekend Digital Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 82% Full Time, 14% Part Time, 1% Temporary, and 3% Contract. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
Digital Verification Engineer

Digital Verification Engineer

Quantum World Technologies Inc

Santa Clara, CA • On-site

$159K - $195K/yr

Contractor

Posted 1 hour ago


Job description

Job Title: Digital Verification Engineer

Job Location: Santa Clara, CA (Onsite for 5 days a week)

Job Type: Long-term contract

Duration: 12 months

Minimum Qualifications

  • The ideal candidate should have a BS/MS in Electrical Engineering 8+ years of experience in hands on digital design verification/Mixed signal Co-simulation in ASIC/SOC products.
  • Advanced knowledge of HVL methodology UVM/OVM, Solid verification skills in problem solving, constrained random testing, and debugging
  • Experience in writing scripts in languages such as Perl or Python
  • Experience in defining coverage space and writing coverage model a plus
  • Experience with SystemVerilog Assertion SVA a plus
  • Familiar with design involving AMBA/APB, AHB, AXI buses
  • Familiar with serial interface protocols SPI/I2C/I3C/UART/MDIO/JTAG
  • Excellent oral and written communication skills.