Job Title: Digital Verification Engineer
Job Location: Santa Clara, CA (Onsite for 5 days a week)
Job Type: Long-term contract
Duration: 12 months
Minimum Qualifications
- The ideal candidate should have a BS/MS in Electrical Engineering 8+ years of experience in hands on digital design verification/Mixed signal Co-simulation in ASIC/SOC products.
- Advanced knowledge of HVL methodology UVM/OVM, Solid verification skills in problem solving, constrained random testing, and debugging
- Experience in writing scripts in languages such as Perl or Python
- Experience in defining coverage space and writing coverage model a plus
- Experience with SystemVerilog Assertion SVA a plus
- Familiar with design involving AMBA/APB, AHB, AXI buses
- Familiar with serial interface protocols SPI/I2C/I3C/UART/MDIO/JTAG
- Excellent oral and written communication skills.