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From Home Digital Verification Engineer Jobs (NOW HIRING)

... home, industrial IoT, and smart cities markets. Learn more atwww.silabs.com. Meet the Team You ... Support automated testing and verification flows through C programming and scripting. * Analyze ...

From military defense and space exploration to biomedical engineering, lives often depend on the ... Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification ...

From military defense and space exploration to biomedical engineering, lives often depend on the ... Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification ...

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From Home Digital Verification Engineer information

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$80K

$142.6K

$203.5K

How much do from home digital verification engineer jobs pay per year?

As of Jun 27, 2026, the average yearly pay for from home digital verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.
What cities are hiring for From Home Digital Verification Engineer jobs? Cities with the most From Home Digital Verification Engineer job openings:
What are the most commonly searched types of Digital Verification Engineer jobs? The most popular types of Digital Verification Engineer jobs are:
What states have the most From Home Digital Verification Engineer jobs? States with the most job openings for From Home Digital Verification Engineer jobs include:
Digital Verification Engineer

Digital Verification Engineer

Quantum World Technologies Inc

Santa Clara, CA • On-site

$159K - $195K/yr

Contractor

Posted 29 days ago


Job description

Job Title: Digital Verification Engineer

Job Location: Santa Clara, CA (Onsite for 5 days a week)

Job Type: Long-term contract

Duration: 12 months

Minimum Qualifications

  • The ideal candidate should have a BS/MS in Electrical Engineering 8+ years of experience in hands on digital design verification/Mixed signal Co-simulation in ASIC/SOC products.
  • Advanced knowledge of HVL methodology UVM/OVM, Solid verification skills in problem solving, constrained random testing, and debugging
  • Experience in writing scripts in languages such as Perl or Python
  • Experience in defining coverage space and writing coverage model a plus
  • Experience with SystemVerilog Assertion SVA a plus
  • Familiar with design involving AMBA/APB, AHB, AXI buses
  • Familiar with serial interface protocols SPI/I2C/I3C/UART/MDIO/JTAG
  • Excellent oral and written communication skills.