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From Home Digital Verification Engineer Jobs (NOW HIRING)

Verification Engineer

Suwanee, GA · Hybrid

$126K/yr

... UVM testbenches from scratch Proficiency with tools such as VCS, Xcelium, Verdi, or similar ... digital verification methodologies Solid debugging and problem-solving skills Preferred ...

Description As a Wireless Radio Verification Engineer, you'll verify Radio digital controllers ... You'll own subsystem verification from test planning through coverage closure, building testbench ...

Senior UVM Digital Verification Engineer

Cambridge, MA · On-site

$113K - $153K/yr

From military defense and space exploration to biomedical engineering, lives often depend on the ... Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification ...

Performs semiconductor design engineering duties including design, development, and testing for ... Collect code and functional coverage results from random simulations, and analyzing uncovered ...

Senior UVM Digital Verification Engineer

Cambridge, MA · On-site

$114K - $156K/yr

From military defense and space exploration to biomedical engineering, lives often depend on the ... Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification ...

Perform professional verification engineering duties in furtherance of architecture and RTL design ... Build verification plans from scratch, build and debug test cases to validate memory controller ...

Perform professional verification engineering duties in furtherance of architecture and RTL design ... Build verification plans from scratch, build and debug test cases to validate memory controller ...

Performs semiconductor design engineering duties including design, development, and testing for ... Collect code and functional coverage results from random simulations, and analyzing uncovered ...

Fiori Technology Solutions is currently hiring for a Design Verification Engineer. This is fulltime ... Digital verification for complex SoC with MCUs (ARM CM0+/CM3/4/CM33) with complex peripherals ...

Digital Verification

Austin, TX · On-site

$150 - $190/hr

Perform professional verification engineering duties in furtherance of architecture and RTL design ... Build verification plans from scratch, build and debug test cases to validate memory controller ...

Showing results 41-60

From Home Digital Verification Engineer information

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How much do from home digital verification engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for from home digital verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

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Infographic showing various From Home Digital Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 2% As Needed, 72% Full Time, 22% Part Time, and 4% Contract. Highlights an 80% Physical, 1% Hybrid, and 19% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Verification Engineer

TRC Talent Solutions

Suwanee, GA • Hybrid

$126K/yr

Full-time

Posted 26 days ago


Job description

Senior Verification Engineer (DDR5 / PMIC / CXL)
Johns Creek, GA (Hybrid/Onsite)


About the Opportunity
Our client, a growing semiconductor organization, has recently expanded its U.S. footprint in the Atlanta area. This is a unique opportunity to join a high-performing engineering team focused on next-generation memory and interconnect solutions supporting data center and cloud infrastructure.
The role offers strong ownership, hands-on technical impact, and meaningful growth within a collaborative global environment.

Role Overview
We are seeking an experienced Verification Engineer to design and develop system-level UVM testbenches for advanced memory and interconnect products, including DDR5 DIMMs, Power Management ICs (PMIC), and CXL-based solutions.
This individual will play a key role in building verification infrastructure, driving system and IP validation, and collaborating across global engineering teams.

Key Responsibilities

Develop and implement UVM/SystemVerilog testbenches for system-level and IP verification
Build verification infrastructure, including stimulus, coverage models, assertions, and scripts
Perform functional verification for memory subsystem and mixed-signal components
Collaborate with design, product, and specification engineering teams
Partner with global verification teams across multiple sites
Debug failing simulations and regression issues
Participate in silicon debug and bring-up activities as needed
Mentor and guide junior engineers


Required Qualifications

BS or MS in Electrical Engineering, Computer Engineering, or related field
5+ years of verification experience in semiconductor environments
Strong hands-on experience building UVM testbenches from scratch
Proficiency with tools such as VCS, Xcelium, Verdi, or similar
Experience with mixed-signal or digital verification methodologies
Solid debugging and problem-solving skills


Preferred Qualifications

Knowledge of DDR5 protocol and/or CXL 2.0 specification
Experience with PMIC or memory subsystem verification
Familiarity with CMOS circuit design fundamentals


Why This Role

Work on cutting-edge memory and interconnect technologies
High visibility and ownership within engineering programs
Collaborative, global team environment
Strong opportunity for career advancement