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Manager Digital Verification Engineer Jobs (NOW HIRING)

Ciena

Digital Verification Engineer Expert

New York, NY · On-site

$147.10K - $234.90K/yr

ASIC Engineer (Digital Verification Engineer Expert (P4)) How You Will Contribute: The Wavelogic ... Possibility of reporting directlyto the Senior Manager as an ASIC Verification Prime * As an ASIC ...

Ciena

Digital Verification Engineer Expert

Manhattan, NY

$147.10K - $234.90K/yr

ASIC Engineer (Digital Verification Engineer Expert (P4)) How You Will Contribute: The Wavelogic ... Possibility of reporting directlyto the Senior Manager as an ASIC Verification Prime * As an ASIC ...

Ciena

Digital Verification Engineer - New Grad

Rochester, NY · On-site

$79.30K - $126.70K/yr

What will you do at Ciena as a Digital Verification Engineer? The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to ...

Luxtera

Digital Verification Engineer

Carlsbad, CA · On-site

$141.10K - $172.20K/yr

This position is for PHY transceiver digital blocks level and chip level verification. ESSENTIAL ... Objected Oriented Programming. * Experience with expertise in the chip level verification ...

Draper

UVM Digital Verification Engineer

Cambridge, MA · On-site

$75K - $156K/yr

... Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this ... Excellent time management skills with the proven ability to meet deadlines * Strong analytical and ...

Protingent

Digital Verification CAD Engineer

San Jose, CA · On-site

$90 - $120/hr

Digital Verification CAD Engineer Position Description : Protingent Staffing has an exciting ... Familiarity with regression management systems and large-scale simulation environments * Exposure ...

Draper

UVM Digital Verification Engineer

Cambridge, MA

$75K - $156K/yr

... Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this ... Excellent time management skills with the proven ability to meet deadlines * Strong analytical and ...

Silabs

Digital Verification Engineer I

Austin, TX · Hybrid

$84K - $156K/yr

Experience with Verilog and SystemVerilogfor digital design and verification through professional setting, internships, coursework, research, or project work. * Programming and scripting experience ...

Silabs

Staff Digital Verification Engineer

Austin, TX · Hybrid

$150.50K - $279.50K/yr

Staff Digital Verification Engineer Austin, TX Meet the Team We arefocused on producingworld ... power management, and best in classlow power wireless modems. We strive to provide advanced ...

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All JobsManager Digital Verification Engineer Jobs

Manager Digital Verification Engineer information

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$105.5K

$149.2K

$167K

How much do manager digital verification engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for manager digital verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Manager Digital Verification Engineer, and why are they important?

To thrive as a Manager Digital Verification Engineer, you need a deep understanding of digital design verification, expertise in SystemVerilog or UVM methodologies, and a relevant engineering degree. Familiarity with industry-standard EDA tools like Synopsys VCS, Cadence Xcelium, and scripting languages such as Python or Perl is critical, along with experience in project management. Strong leadership, communication, and problem-solving abilities help you effectively guide teams and collaborate across departments. These skills ensure efficient, high-quality verification processes, timely project delivery, and successful team performance in complex semiconductor development environments.

How does a Manager Digital Verification Engineer typically balance hands-on technical verification work with team leadership responsibilities?

A Manager Digital Verification Engineer often splits their time between overseeing the technical direction of verification projects and managing a team of engineers. While they remain involved in high-level planning, reviewing verification strategies, and resolving complex technical issues, they also focus on mentoring team members, conducting performance reviews, and aligning resources to project timelines. The role requires strong organizational skills to ensure project milestones are met without sacrificing team development or quality. Regular collaboration with design, validation, and project management teams is essential to ensure seamless integration and product delivery.

What does a Manager Digital Verification Engineer do?

A Manager Digital Verification Engineer leads a team responsible for verifying the functionality and performance of digital hardware designs, ensuring they meet specifications before production. This role involves overseeing the development and execution of verification plans using simulation, emulation, and formal verification tools. The manager coordinates with design, validation, and project management teams to deliver high-quality, bug-free silicon products on schedule. They also mentor engineers, optimize verification methodologies, and maintain project documentation.

What is the difference between Manager Digital Verification Engineer vs Digital Verification Engineer?

AspectManager Digital Verification EngineerDigital Verification Engineer
CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related; often with leadership experienceBachelor's/Master's in Electrical Engineering, VLSI, or related; no managerial experience required
Work EnvironmentLeads verification teams, manages projects, coordinates with design teamsPerforms verification tasks, runs simulations, develops testbenches
Industry UsageCommon in semiconductor, electronics, and chip design companiesWidely used in similar industries for verification roles

The main difference is that a Manager Digital Verification Engineer oversees verification teams and projects, focusing on leadership and coordination, while a Digital Verification Engineer primarily executes verification tasks and develops test environments. The managerial role involves more strategic planning, resource management, and team leadership, whereas the verification engineer role is more technical and hands-on.

What cities are hiring for Manager Digital Verification Engineer jobs? Cities with the most Manager Digital Verification Engineer job openings:
What are the most commonly searched types of Digital Verification Engineer jobs? The most popular types of Digital Verification Engineer jobs are:
What states have the most Manager Digital Verification Engineer jobs? States with the most job openings for Manager Digital Verification Engineer jobs include:
Manager Digital Verification Engineer jobs near you
Infographic showing various Manager Digital Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 80% Full Time, 10% Part Time, and 10% Contract. Highlights an 85% Physical, 7% Hybrid, and 8% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.
Digital Verification Engineer

Digital Verification Engineer

Quantum World Technologies Inc

Santa Clara, CA • On-site

$159.70K - $195K/yr

Contractor

Posted 29 days ago

Job description

Job Title: Digital Verification Engineer

Job Location: Santa Clara, CA (Onsite for 5 days a week)

Job Type: Long-term contract

Duration: 12 months

Minimum Qualifications

  • The ideal candidate should have a BS/MS in Electrical Engineering 8+ years of experience in hands on digital design verification/Mixed signal Co-simulation in ASIC/SOC products.
  • Advanced knowledge of HVL methodology UVM/OVM, Solid verification skills in problem solving, constrained random testing, and debugging
  • Experience in writing scripts in languages such as Perl or Python
  • Experience in defining coverage space and writing coverage model a plus
  • Experience with SystemVerilog Assertion SVA a plus
  • Familiar with design involving AMBA/APB, AHB, AXI buses
  • Familiar with serial interface protocols SPI/I2C/I3C/UART/MDIO/JTAG
  • Excellent oral and written communication skills.