ZipRecruiter

Log In

1

Manager Digital Verification Engineer Jobs in Chicago, IL

Eliyan

DV - Director of Design Verification

Mundelein, IL · On-site

$138K - $169K/yr

Build, mentor, and manage a world-class verification team; establish best practices for UVM-based ... D in Electrical Engineering, Computer Engineering, or related fields * 15+ years of experience in ...

cap

Manager Digital Content

Winnetka, IL · On-site

Brief Description The Manager, Digital Content is responsible for: Advancing the CAP's digital ... Partner with content contributors, UX, developers, business owners, and agency partners to improve ...

Omnicom

Manager, Digital Activation

Chicago, IL · On-site

$92K - $119K/yr

Performance Media As a Manager, Digital Activation you are entrusted with the responsibility of ... third-party verification tools, including DoubleVerifyIllinois: $50,000.00-$95,000.00 Omnicom ...

AbbVie

Senior Design Verification Engineer I

North Chicago, IL · On-site

$100K - $138K/yr

As a Senior Scientist I, Engineering - Design Verification Engineer you would be part of a multi ... Experience with design control, risk management, and regulatory standards including ISO compliance ...

AbbVie

Senior Design Verification Engineer I

North Chicago, IL · On-site

$100K - $138K/yr

As a Senior Scientist I, Engineering - Design Verification Engineer you would be part of a multi ... Experience with design control, risk management, and regulatory standards including ISO compliance ...

Baxter

Product Manager, Digital Health

Deerfield, IL · On-site

Your Role As the Product Manager, Digital Health, you will define, develop, and deliver software ... Partner with Engineering and UX teams to deliver software products and features using Agile ...

next page

Showing results 1-20

All JobsDigital Verification Engineer JobsManager Digital Verification Engineer JobsManager Digital Verification Engineer Jobs in Chicago, IL

Manager Digital Verification Engineer information

See Chicago, IL salary details

$108.7K

$153.6K

$172K

How much do manager digital verification engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for manager digital verification engineer in Chicago, IL is $153,646.00, according to ZipRecruiter salary data. Most workers in this role earn between $140,100.00 and $171,000.00 per year, depending on experience, location, and employer.

What is the difference between Manager Digital Verification Engineer vs Digital Verification Engineer?

AspectManager Digital Verification EngineerDigital Verification Engineer
CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related; often with leadership experienceBachelor's/Master's in Electrical Engineering, VLSI, or related; no managerial experience required
Work EnvironmentLeads verification teams, manages projects, coordinates with design teamsPerforms verification tasks, runs simulations, develops testbenches
Industry UsageCommon in semiconductor, electronics, and chip design companiesWidely used in similar industries for verification roles

The main difference is that a Manager Digital Verification Engineer oversees verification teams and projects, focusing on leadership and coordination, while a Digital Verification Engineer primarily executes verification tasks and develops test environments. The managerial role involves more strategic planning, resource management, and team leadership, whereas the verification engineer role is more technical and hands-on.

What does a manager digital verification engineer do?

A Manager Digital Verification Engineer leads a team responsible for verifying the functionality and performance of digital hardware designs, ensuring they meet specifications before production. This role involves overseeing the development and execution of verification plans using simulation, emulation, and formal verification tools. The manager coordinates with design, validation, and project management teams to deliver high-quality, bug-free silicon products on schedule. They also mentor engineers, optimize verification methodologies, and maintain project documentation.

What are the key skills and qualifications needed to thrive as a manager digital verification engineer, and why are they important?

To thrive as a Manager Digital Verification Engineer, you need a deep understanding of digital design verification, expertise in SystemVerilog or UVM methodologies, and a relevant engineering degree. Familiarity with industry-standard EDA tools like Synopsys VCS, Cadence Xcelium, and scripting languages such as Python or Perl is critical, along with experience in project management. Strong leadership, communication, and problem-solving abilities help you effectively guide teams and collaborate across departments. These skills ensure efficient, high-quality verification processes, timely project delivery, and successful team performance in complex semiconductor development environments.

How does a manager digital verification engineer typically balance hands-on technical verification work with team leadership responsibilities?

A Manager Digital Verification Engineer often splits their time between overseeing the technical direction of verification projects and managing a team of engineers. While they remain involved in high-level planning, reviewing verification strategies, and resolving complex technical issues, they also focus on mentoring team members, conducting performance reviews, and aligning resources to project timelines. The role requires strong organizational skills to ensure project milestones are met without sacrificing team development or quality. Regular collaboration with design, validation, and project management teams is essential to ensure seamless integration and product delivery.
What are the most commonly searched types of Digital Verification Engineer jobs in Chicago, IL? The most popular types of Digital Verification Engineer jobs in Chicago, IL are:
Manager Digital Verification Engineer jobs near you
Infographic showing various Manager Digital Verification Engineer job openings in Chicago, IL as of June 2026, with employment types broken down into 99% Full Time, and 1% Contract. Highlights an 92% Physical, 3% Hybrid, and 5% Remote job distribution, with an average salary of $153,646 per year, or $73.9 per hour.

DV - Director of Design Verification

Eliyan

Mundelein, IL • On-site

$138K - $169K/yr

Full-time

Re-posted 24 days ago

Job description

Join the leading chiplet startup! As the Director of Design Verification at Eliyan, you will lead and scale a high-performing verification team at a fast-paced startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will own the end-to-end verification strategy across multiple PHY and controller products, spanning link layer, PCS, PMA, forward error correction, and analog/mixed-signal verification flows. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities:
  • Define and own the verification strategy and methodology across multiple PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces
  • Build, mentor, and manage a world-class verification team; establish best practices for UVM-based environments, coverage-driven verification, and formal methods
  • Drive verification planning and execution for link layer, PCS, PMA, forward error correction (FEC), auto-negotiation, and link training subsystems
  • Establish and champion analog/mixed-signal (AMS) verification flows, including real-number modeling (RNM), SVAMS co-simulation strategies, and integration of AMS behavioral models into digital verification environments
  • Partner with design, architecture, DFT, and physical design teams to drive micro-architecture reviews, test-plan completeness, and functional/code/assertion coverage closure
  • Own verification milestones and deliverables across multiple concurrent tapeout programs; track progress, manage risk, and report status to executive leadership
  • Drive continuous improvement in verification infrastructure including regression frameworks, CI/CD integration, coverage analytics, and productivity tooling
  • Ensure IP compliance with relevant industry standards including IEEE 802.3, UCIe, and emerging D2D interconnect specifications
  • Evaluate, integrate, and manage 3rd party VIPs and AMS verification IP; coordinate feature/bug tracking and vendor relationships
  • Oversee development of DPI-based firmware co-simulation environments and system-level verification strategies for PHY bring-up and validation
  • Oversee GLS environments for functional, timing, and power-aware simulations; drive signoff quality for tapeout readiness
Qualifications:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 15+ years of experience in design verification of high-speed serial interfaces, PHYs, and controller IPs, with at least 5 years in a people-management or leadership role
  • Deep expertise in SystemVerilog/UVM methodology, constrained-random verification, assertion-based verification, and formal verification techniques
  • Demonstrated experience with AMS verification methodologies including real-number modeling (RNM), Verilog-AMS, SVAMS co-simulation, and mixed-signal behavioral modeling
  • Strong working knowledge of link layer protocols, PCS architectures (including FEC — RS-FEC, KP4, KR4), Ethernet 802.3 clauses for 100G/200G/400G/800G, and die-to-die interconnect standards such as UCIe
  • Proven ability to drive verification innovation including automation, AI/ML-assisted verification, and scalable methodologies that improve team productivity and product quality
  • Hands-on experience verifying mixed-signal IPs (PLLs, CDRs, SerDes analog front-ends, DLLs) and integrating analog models into digital verification environments
  • Track record of successfully building and scaling verification teams in startup or high-growth environments with multiple concurrent tapeouts
  • Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect verification a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.