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Assistant Digital Verification Engineer Jobs in Chicago, IL

Eliyan

DV - Director of Design Verification

Mundelein, IL · On-site

$138K - $169K/yr

... into digital verification environments * Partner with design, architecture, DFT, and physical ... D in Electrical Engineering, Computer Engineering, or related fields * 15+ years of experience in ...

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL

$138K/yr

D in Electrical Engineering, Computer Engineering, or related fields * 12+ years of experience in ... verification signals in application materials based on available information. These tools assist ...

Baxter & Woodman

Digital Water Engineer I

Chicago, IL

$74K - $90K/yr

Digital Water Engineer I Location Options: Crystal Lake, Chicago, Naperville, Bannockburn, or ... Digital & AI Responsibilities: * Assist in the development and implementation of AI and machine ...

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Assistant Digital Verification Engineer information

See Chicago, IL salary details

$34K

$91.4K

$138.6K

How much do assistant digital verification engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for assistant digital verification engineer in Chicago, IL is $91,430.00, according to ZipRecruiter salary data. Most workers in this role earn between $72,600.00 and $107,600.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an assistant digital verification engineer, and why are they important?

To thrive as an Assistant Digital Verification Engineer, you need a solid understanding of digital design fundamentals, computer architecture, and a relevant degree in electrical or computer engineering. Familiarity with verification languages like SystemVerilog or UVM, along with experience using simulation and debugging tools such as ModelSim or VCS, is typically required. Strong analytical thinking, problem-solving ability, and effective communication skills help you collaborate with design teams and troubleshoot complex issues. These skills and qualities are crucial for ensuring reliable hardware designs and seamless project execution in a fast-paced engineering environment.

What are some common challenges faced by an assistant digital verification engineer during the verification process?

One common challenge for Assistant Digital Verification Engineers is ensuring comprehensive test coverage while meeting tight project deadlines. Balancing the need to identify edge cases and potential design bugs with limited simulation time can be demanding. Collaborating effectively with design and verification teams to clarify specifications and debug complex issues is also essential. Adapting quickly to evolving verification methodologies and tools is key to success in this role.

What is the difference between Assistant Digital Verification Engineer vs Digital Verification Engineer?

AspectAssistant Digital Verification EngineerDigital Verification Engineer
Required CredentialsBachelor's degree in Electrical Engineering or related field; some certificationsBachelor's or Master's degree; professional certifications often preferred
Work EnvironmentEntry-level, team support, supervised tasksMore independent, complex verification tasks
Employer & Industry UsageSemiconductor, electronics companies, R&D teamsSame industries, higher responsibility roles

The Assistant Digital Verification Engineer typically supports verification activities under supervision, focusing on learning and assisting with testing processes. In contrast, the Digital Verification Engineer handles more complex verification tasks independently, ensuring the functionality of digital designs. Both roles are essential in the verification process, but they differ in experience level and responsibility.

What does an assistant digital verification engineer do?

An Assistant Digital Verification Engineer supports the design and testing of digital circuits and systems to ensure they function correctly according to specifications. They assist in creating verification plans, writing and running simulations, debugging issues, and documenting results. Their work is essential in identifying design flaws early in the development process, which helps to improve the quality and reliability of electronic products. Typically, they work closely with design engineers and senior verification engineers as part of a larger hardware development team.
What are the most commonly searched types of Digital Verification Engineer jobs in Chicago, IL? The most popular types of Digital Verification Engineer jobs in Chicago, IL are:
Assistant Digital Verification Engineer jobs near you

DV - Director of Design Verification

Eliyan

Mundelein, IL • On-site

$138K - $169K/yr

Full-time

Re-posted 24 days ago

Job description

Join the leading chiplet startup! As the Director of Design Verification at Eliyan, you will lead and scale a high-performing verification team at a fast-paced startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will own the end-to-end verification strategy across multiple PHY and controller products, spanning link layer, PCS, PMA, forward error correction, and analog/mixed-signal verification flows. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities:
  • Define and own the verification strategy and methodology across multiple PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces
  • Build, mentor, and manage a world-class verification team; establish best practices for UVM-based environments, coverage-driven verification, and formal methods
  • Drive verification planning and execution for link layer, PCS, PMA, forward error correction (FEC), auto-negotiation, and link training subsystems
  • Establish and champion analog/mixed-signal (AMS) verification flows, including real-number modeling (RNM), SVAMS co-simulation strategies, and integration of AMS behavioral models into digital verification environments
  • Partner with design, architecture, DFT, and physical design teams to drive micro-architecture reviews, test-plan completeness, and functional/code/assertion coverage closure
  • Own verification milestones and deliverables across multiple concurrent tapeout programs; track progress, manage risk, and report status to executive leadership
  • Drive continuous improvement in verification infrastructure including regression frameworks, CI/CD integration, coverage analytics, and productivity tooling
  • Ensure IP compliance with relevant industry standards including IEEE 802.3, UCIe, and emerging D2D interconnect specifications
  • Evaluate, integrate, and manage 3rd party VIPs and AMS verification IP; coordinate feature/bug tracking and vendor relationships
  • Oversee development of DPI-based firmware co-simulation environments and system-level verification strategies for PHY bring-up and validation
  • Oversee GLS environments for functional, timing, and power-aware simulations; drive signoff quality for tapeout readiness
Qualifications:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 15+ years of experience in design verification of high-speed serial interfaces, PHYs, and controller IPs, with at least 5 years in a people-management or leadership role
  • Deep expertise in SystemVerilog/UVM methodology, constrained-random verification, assertion-based verification, and formal verification techniques
  • Demonstrated experience with AMS verification methodologies including real-number modeling (RNM), Verilog-AMS, SVAMS co-simulation, and mixed-signal behavioral modeling
  • Strong working knowledge of link layer protocols, PCS architectures (including FEC — RS-FEC, KP4, KR4), Ethernet 802.3 clauses for 100G/200G/400G/800G, and die-to-die interconnect standards such as UCIe
  • Proven ability to drive verification innovation including automation, AI/ML-assisted verification, and scalable methodologies that improve team productivity and product quality
  • Hands-on experience verifying mixed-signal IPs (PLLs, CDRs, SerDes analog front-ends, DLLs) and integrating analog models into digital verification environments
  • Track record of successfully building and scaling verification teams in startup or high-growth environments with multiple concurrent tapeouts
  • Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect verification a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.