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Weekend Digital Verification Engineer Jobs (NOW HIRING)

Apple

Wireless Radio Verification Engineer

San Diego, CA

$120.30K - $210.10K/yr

As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... This role emphasizes digital verification while bridging to RF/analog domains-you'll work closely ...

Apple

Wireless Radio Verification Engineer

San Diego, CA

$120.30K - $210.10K/yr

As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... This role emphasizes digital verification while bridging to RF/analog domains-you'll work closely ...

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All JobsWeekend Digital Verification Engineer Jobs

Weekend Digital Verification Engineer information

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$142.6K

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How much do weekend digital verification engineer jobs pay per year?

As of May 29, 2026, the average yearly pay for weekend digital verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.
What are the most commonly searched types of Digital Verification Engineer jobs? The most popular types of Digital Verification Engineer jobs are:
Weekend Digital Verification Engineer jobs near you
Infographic showing various Weekend Digital Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 67% Full Time, 29% Part Time, and 3% Contract. Highlights an 92% Physical, 5% Hybrid, and 3% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Mixed-Signal Verification Engineer

Chelsea Search Group

Dallas, TX

$134.60K/yr

Full-time

Posted 15 days ago

Job description

We are seeking a highly motivated Mixed-Signal Verification Engineer III to support verification of analog and mixed-signal IP integrated within digital-on-top SoC environments. Reporting to the Analog Design Team Manager, this individual contributor role will lead development and execution of verification strategies for complex power, clocking, and mixed-signal subsystems prior to tape-out. The ideal candidate brings strong expertise in SystemVerilog, UVM methodologies, and behavioral modeling, along with hands-on experience verifying analog IP in large-scale SoC environments.
Key Responsibilities
• Lead mixed-signal verification activities for analog IP blocks using SystemVerilog and UVM-based methodologies.
• Develop scalable digital-on-top verification environments and testbenches incorporating behavioral models for analog IP including PLLs, LDOs, oscillators, DC/DC converters, and related circuitry.
• Translate analog and mixed-signal specifications into comprehensive verification plans, assertions, coverage models, and checkers.
• Create and maintain behavioral models using SystemVerilog real-number modeling (RNM) and/or Verilog-AMS for efficient system-level simulation.
• Execute regression testing, analyze failures, and debug issues across analog, digital, and mixed-signal domains.
• Verify configuration, calibration, monitoring, protection, and fault-handling interfaces between analog IP and digital control logic.
• Collaborate closely with analog designers, digital verification engineers, and system architects to ensure verification completeness and tape-out readiness.
Behavioral Modeling & Abstraction
• Develop high-level functional and behavioral models optimized for large-scale SoC simulation while maintaining key analog performance characteristics.
• Define modeling assumptions, validation approaches, and abstraction strategies in partnership with analog design teams.
• Contribute to mixed-signal co-simulation methodologies balancing simulation accuracy, runtime efficiency, and model reuse.
Tools, Methodologies & Quality
• Utilize industry-standard digital, mixed-signal, and AMS simulation and verification tools.
• Apply coverage-driven and assertion-based verification methodologies to ensure robust design validation.
• Participate in design and verification reviews while adhering to established regression, version control, and documentation practices.
• Identify and implement opportunities for workflow automation and verification flow improvements.
Collaboration & Technical Leadership
• Work independently on complex verification assignments while providing mentorship to junior engineers.
• Contribute verification expertise during IP architecture, integration, and design reviews.
• Proactively identify technical risks, communicate issues effectively, and drive resolution across cross-functional teams.
Minimum Qualifications
• Bachelor’s or Master’s degree in Electrical Engineering or a related technical discipline.
• 6+ years of experience in mixed-signal and/or digital IC verification.
• Strong proficiency with SystemVerilog and UVM-based verification methodologies.
• Hands-on experience developing behavioral models using Verilog-AMS and/or SystemVerilog real-number modeling.
• Experience verifying analog and mixed-signal IP within digital-on-top SoC environments.
Preferred Qualifications
• Familiarity with power management and clocking architectures including bandgaps, PLLs, LDOs, oscillators, and DC/DC converters.
• Experience with coverage-driven verification, assertions, and formal verification concepts.
• Exposure to automotive, industrial, or safety-critical semiconductor development environments.
• Experience with scripting, automation, or AI-assisted verification workflows.