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Senior Digital Verification Engineer Jobs (NOW HIRING)

Renesas Electronics

Senior Digital Engineer

Chandler, AZ · On-site

$133K/yr

Company Description Renesas Electronics is seeking a skilled and motivated Senior Digital Design ... Work closely with Analog and Verification engineers to deliver high-quality silicon solutions.

Renesas Electronics

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

Company Description Renesas Electronics is seeking a skilled and motivated Senior Digital Design ... Work closely with Analog and Verification engineers to deliver high-quality silicon solutions.

HII's Mission Technologies division

$116K - $190K/yr

Senior This opportunity resides with Warfare Systems (WS) , a business group within HII's Mission ... Engineering, Computer Science, or a related field Experience with modern digital verification and ...

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Senior Digital Verification Engineer information

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$70.5K

$134.6K

$195K

How much do senior digital verification engineer jobs pay per year?

As of Jul 20, 2026, the average yearly pay for senior digital verification engineer in the United States is $134,577.00, according to ZipRecruiter salary data. Most workers in this role earn between $107,500.00 and $157,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Senior Digital Verification Engineer, and why are they important?

To thrive as a Senior Digital Verification Engineer, you need expertise in digital design verification methodologies, strong knowledge of hardware description languages (such as Verilog/SystemVerilog), and typically a bachelor's or master's degree in electrical or computer engineering. Proficiency with tools like UVM (Universal Verification Methodology), simulation environments (e.g., Mentor Questa, Synopsys VCS), and scripting languages (Python, Perl, TCL) is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design teams and troubleshoot complex issues. These skills ensure robust verification processes, reducing design errors and enabling the successful delivery of reliable, high-performance digital products.

How does a Senior Digital Verification Engineer typically collaborate with design and software teams during the verification process?

Senior Digital Verification Engineers work closely with both hardware design and software development teams to ensure that digital circuits meet all specifications and function correctly. They often participate in regular cross-functional meetings to align on design intent, clarify requirements, and address any ambiguities early in the development cycle. Effective collaboration involves sharing test plans, debugging issues together, and providing feedback to refine both hardware and firmware. This collaborative approach helps streamline verification cycles and catch issues before they become costly to fix.

What does a Senior Digital Verification Engineer do?

A Senior Digital Verification Engineer is responsible for ensuring the correctness and quality of complex digital integrated circuits or systems before they are manufactured. They develop and implement verification plans, create testbenches, write test cases, and run simulations to catch design flaws early in the development process. These engineers often use hardware description languages like SystemVerilog and verification methodologies such as UVM. Additionally, they collaborate closely with design engineers and other team members to debug issues and improve design reliability.
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Senior Digital Verification Engineer jobs near you
Infographic showing various Senior Digital Verification Engineer job openings in the United States as of July 2026, with employment types broken down into 87% Full Time, 11% Part Time, and 2% Contract. Highlights an 90% Physical, 2% Hybrid, and 8% Remote job distribution, with an average salary of $134,577 per year, or $64.7 per hour.

Digital Design Verification Engineer

Olix Computing

Austin, TX • On-site

£123K/yr

Full-time

Retirement

Re-posted yesterday

Job description

About OLIX
AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.
The Role
We are seeking highly skilled and motivated Senior / Staff Digital Verification Engineers with a strong background in CMOS digital design and verification to take ownership of the functional correctness of high-speed, real-time data-processing silicon, from early algorithm modelling through verified RTL, sign-off, and silicon bring-up.
You will join a multidisciplinary group creating groundbreaking hardware where digital, optical, and mixed-signal domains intersect.
The ideal candidate brings deep expertise in digital verification methodologies, a solid understanding of hardware architecture, and a passion for building provably correct, high-performance systems that underpin breakthrough AI hardware.
Responsibilities
  • Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, deep pipelining, and robust hand-shaking in advanced CMOS nodes
  • Develop and maintain comprehensive verification environments using SystemVerilog/UVM, including constrained-random testing, coverage closure, and regression automation
  • Define and implement assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance
  • Apply formal verification techniques (property checking, assertions, equivalence checking) to complement simulation-based verification and accelerate bug discovery
  • Model and validate algorithms using MATLAB/Simulink or Python, ensuring functional equivalence from algorithmic models through RTL and gate-level sign-off
  • Support FPGA prototyping and silicon bring-up by developing targeted testcases, debug strategies, and post-silicon validation plans
  • Collaborate closely with digital design, optical-hardware, mixed-signal, and software teams to ensure correct integration across clock domains, interfaces, and firmware abstractions
  • Analyse verification results to identify root causes, drive design fixes, and improve verification efficiency and reuse
  • Contribute to verification methodology development, documentation, and design/verification reviews; mentor junior engineers where appropriate

Skills & Experience
  • 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs
  • Ownership of verification for at least one complex block or subsystem processing continuous real-time data streams
  • Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (e.g. UVM. CocoTB)
  • Proven experience verifying designs operating in GHz-class clock domains, including CDC/RDC analysis
  • Familiarity with industry-standard EDA flows: RTL simulation, formal verification, linting, CDC/RDC, STA, power-intent (UPF/CPF), and gate-level simulation
  • Experience verifying high-speed IP such as SerDes, DDR/HBM, PCIe, Ethernet, or similar interfaces
  • Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis, and test-vector generation
  • Solid grounding in digital design principles, computer architecture, DSP fundamentals, and semiconductor basics
  • Clear communicator who collaborates effectively across disciplines and is comfortable operating in a fast-moving, evolving environment

Nice to have
  • Tape-out experience at 22 nm or below
  • Deep hands-on experience with formal verification methodologies, including property decomposition, and coverage-driven formal on tools such as Jasper
  • Exposure to coherent optical links or photonic-electronic co-design
  • Familiarity with AI/ML workloads, systolic arrays, or tensor-processing architectures
  • Expertise in arithmetic pipeline verification
  • Expertise in processor and ISA verification
  • Contributions to open-source RTL, verification frameworks, or FPGA platforms

Compensation & Equity
  • Competitive Salary: Commensurate with your experience, skills, and location
  • Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it
  • Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
  • Retirement Benefits:Employer-contributed retirement plans to help you build long-term financial security.

Due to U.S. export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

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