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Automation Verification Engineer Jobs (NOW HIRING)

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141K/yr

Create test benches, test cases, and automation frameworks in System Verilog. * Analyze test ... Engineering, or related fields. * 10 years of experience in UVM-based verification of FPGA systems.

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1063 Location: Austin, TX More about this job > Description Design ... Powered by ApplicantStack Hiring Automation Software Privacy Policy | Terms of Use

Correct Designs

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Design Verification Engineer ID: 1058 Location: Austin, TX More about this job > Description Design ... Powered by ApplicantStack Hiring Automation Software Privacy Policy | Terms of Use

Socket.dev

Senior Verification Engineer

Boston, MA · On-site

$90K - $165K/yr

A Verification Engineer is a technical position responsible for testing and verification of ... Test tools and test automation experience * Understanding of software Development lifecycle and ...

Socket.dev

Senior Verification Engineer

Minneapolis, MN · On-site

$90K - $165K/yr

A Verification Engineer is a technical position responsible for testing and verification of ... Test tools and test automation experience * Understanding of software Development lifecycle and ...

Full Spectrum

Senior Verification Engineer

Boston, MA · On-site

$90K - $165K/yr

A Verification Engineer is a technical position responsible for testing and verification of ... and test automation experience · Understanding of software Development lifecycle and Agile ...

Intel Corporation

$105K - $200K/yr

Develop automation scripts and tools using Python, Perl, C++, or similar languages to optimize ... developers, and physical design teams to verify complex architectural features * Maintain and ...

Intel Corporation

CPU Verification Engineer

Austin, TX · On-site

$134K/yr

The Role and Impact As a CPU Design Verification Engineer , you'll play a pivotal role in ensuring ... Develop automation scripts and tools using Python, Perl, C++, or similar languages to optimize ...

Intel Corporation

CPU Verification Engineer

Austin, TX · On-site

$105K - $200K/yr

Develop automation scripts and tools using Python, Perl, C++, or similar languages to optimize ... developers, and physical design teams to verify complex architectural features * Maintain and ...

Automated Systems, Inc.

Be Seen First

Senior Automation Engineer

Kenosha, WI · On-site

$65 - $85/hr

Senior Automation Engineer - Device Assembly & Packaging Engagement : Contract assignment through ... The role spans architecture and design review through FAT, SAT, automation verification ...

IC Enable

AMS Verification Engineer

Richardson, TX · On-site +1

$122K/yr

You will develop verification plans, build and debug mixed-signal testbenches, run simulations ... Programming or automation experience with Python, Perl, Tcl, or SKILL * Experience with sensor ...

Nutanix

GSoC Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Contribute to methodology improvements, automation, reusable verification components, and AI-assisted verification flows.Develop AI agents that automate engineering tasks across domains workflows.

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As of Sep 13, 2026, the average yearly pay for automation verification engineer in the United States is $107,126.00, according to ZipRecruiter salary data. Most workers in this role earn between $86,500.00 and $123,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Automation Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $107,126 per year, or $51.5 per hour.

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ • On-site

Airspan
See more jobs at Airspanexternal

$141K/yr

Full-time

Re-posted 5 days ago

Job description

Airspan Careers
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Location: Warren, New Jersey, Plano, TX or REMOTE U.S.
Company: AirSpan Networks
About AirSpan
AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies.
Job Description
As a UVM Verification Engineer, you will be responsible for developing and executing test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of AirSpan's ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards.
Key Responsibilities
  • Develop and implement UVM-based verification plans and test strategies for FPGA designs.
  • Perform functional, system-level, and regression testing for digital hardware components.
  • Create test benches, test cases, and automation frameworks in System Verilog.
  • Analyze test results, debug issues, and collaborate with design teams to resolve defects.
  • Ensure compliance with industry standards and customer requirements.
  • Provide documentation and reports on test procedures, results, and defect tracking.
  • Continuously optimize test processes and tools to improve efficiency and accuracy.

Qualifications & Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
  • 10 years of experience in UVM-based verification of FPGA systems.
  • Strong understanding of SystemVerilog and Universal Verification Methodology (UVM).
  • Proficiency in scripting languages such as Python or Perl for automation.
  • Experience with simulation tools such as ModelSim or QuestaSim.
  • Experience with C/C++
  • Experience in implementing Bit Accurate Models and debugging DSP designs
  • Familiarity with debugging tools, coverage metrics, and formal verification techniques.
  • Strong problem-solving and analytical skills with attention to detail.
  • Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
  • Ability to work collaboratively in a fast-paced, cross-functional team environment.
  • Design experience a plus.

Preferred Skills
  • Experience in verification of communication protocols.
  • Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.
  • Understanding of hardware/software co-verification techniques.

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