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Digital Verification Engineer Jobs in Illinois (NOW HIRING)

Eliyan

DV - Director of Design Verification

Mundelein, IL

$138K - $169K/yr

... into digital verification environments * Partner with design, architecture, DFT, and physical ... D in Electrical Engineering, Computer Engineering, or related fields * 15+ years of experience in ...

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL · On-site

$138K/yr

D in Electrical Engineering, Computer Engineering, or related fields * 12+ years of experience in ... verification signals in application materials based on available information. These tools assist ...

AHEAD

Product Engineer 1

Libertyville, IL · On-site

AHEAD builds platforms for digital business. By weaving together advances in cloud infrastructure ... Collaborate with Manufacturing Engineering, System Verification engineering, to ensure proper ...

AHEAD

Product Engineer 1

Libertyville, IL · On-site

$80K - $120K/yr

AHEAD builds platforms for digital business. By weaving together advances in cloud infrastructure ... Collaborate with Manufacturing Engineering, System Verification engineering, to ensure proper ...

AHEAD

Product Engineer 1

Libertyville, IL · On-site

AHEAD builds platforms for digital business. By weaving together advances in cloud infrastructure ... Collaborate with Manufacturing Engineering, System Verification engineering, to ensure proper ...

Caterpillar

Principal Digital Project Manager

Peoria, IL · On-site

$147K - $240K/yr

Guide cross-functional teams in project execution using software engineering knowledge and business ... Review and verify data accuracy, track software quality issues, and support end users. Use Gantt ...

Baxter

Senior Systems Engineer

Round Lake, IL · On-site

$96K - $132K/yr

Work with verification engineers to define test strategies for the development of verification ... Digital Interface, Fluid Mechanics, Materials Science, etc. Success in delivering results on ...

SwiftCruit

Principal Systems Engineer

Round Lake, IL · On-site

$112 - $154/hr

Work with verification engineers to define test strategies for the development of verification ... Digital Interface, Fluid Mechanics, Materials Science, etc. * Success in delivering results on ...

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All JobsDigital Verification Engineer JobsDigital Verification Engineer Jobs in Illinois

Digital Verification Engineer information

See Illinois salary details

$102.2K

$144.5K

$161.8K

How much do digital verification engineer jobs pay per year?

As of Aug 13, 2026, the average yearly pay for digital verification engineer in Illinois is $144,530.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,800.00 and $160,900.00 per year, depending on experience, location, and employer.

What is a digital verification engineer?

A Digital Verification Engineer is responsible for ensuring the correctness of digital designs before manufacturing. They develop and implement testbenches using hardware description languages like SystemVerilog and methodologies like UVM. Their role involves writing test cases, debugging failures, and improving verification efficiency. The goal is to identify design issues early in the development cycle, reducing costly revisions.

What are the key skills and qualifications needed to thrive as a digital verification engineer?

To thrive as a Digital Verification Engineer, you need a solid background in digital design, computer engineering, and experience with verification methodologies, often supported by a Bachelor’s or Master’s degree in a related field. Proficiency with hardware description languages (such as Verilog, VHDL), simulation tools (like ModelSim, Questa), scripting languages (Python, Perl), and familiarity with standard verification methodologies (UVM, SystemVerilog) are typically required. Attention to detail, strong analytical thinking, and effective communication skills are crucial soft skills for collaborating with design teams and troubleshooting complex systems. These abilities ensure accurate verification outcomes, minimize design errors, and facilitate seamless teamwork in fast-paced semiconductor environments.

What are some common daily responsibilities for a digital verification engineer?

As a Digital Verification Engineer, your daily tasks typically include developing and maintaining testbenches, writing and executing test cases, and analyzing simulation results to identify potential design issues. You’ll work closely with design engineers to review specifications and debug hardware or firmware discrepancies, ensuring that the digital designs meet all functional and timing requirements. Collaborating within cross-functional teams and participating in regular code reviews are also standard parts of the workflow. This hands-on and collaborative environment helps accelerate product development and ensures high-quality deliverables.

What are the most commonly searched types of Digital Verification Engineer jobs in Illinois? The most popular types of Digital Verification Engineer jobs in Illinois are:
What are popular job titles related to Digital Verification Engineer jobs in Illinois? For Digital Verification Engineer jobs in Illinois, the most frequently searched job titles are:
What job categories do people searching Digital Verification Engineer jobs in Illinois look for? The top searched job categories for Digital Verification Engineer jobs in Illinois are:
Digital Verification Engineer jobs near you
Infographic showing various Digital Verification Engineer job openings in Illinois as of August 2026, with employment types broken down into 1% Internship, 83% Full Time, 12% Part Time, 1% Temporary, and 3% Contract. Highlights an 87% Physical, 4% Hybrid, and 9% Remote job distribution, with an average salary of $144,530 per year, or $69.5 per hour.

DV - Director of Design Verification

Eliyan

Mundelein, IL

$138K - $169K/yr

Full-time

Re-posted 27 days ago

Job description

Join the leading chiplet startup! As the Director of Design Verification at Eliyan, you will lead and scale a high-performing verification team at a fast-paced startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will own the end-to-end verification strategy across multiple PHY and controller products, spanning link layer, PCS, PMA, forward error correction, and analog/mixed-signal verification flows. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities:
  • Define and own the verification strategy and methodology across multiple PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces
  • Build, mentor, and manage a world-class verification team; establish best practices for UVM-based environments, coverage-driven verification, and formal methods
  • Drive verification planning and execution for link layer, PCS, PMA, forward error correction (FEC), auto-negotiation, and link training subsystems
  • Establish and champion analog/mixed-signal (AMS) verification flows, including real-number modeling (RNM), SVAMS co-simulation strategies, and integration of AMS behavioral models into digital verification environments
  • Partner with design, architecture, DFT, and physical design teams to drive micro-architecture reviews, test-plan completeness, and functional/code/assertion coverage closure
  • Own verification milestones and deliverables across multiple concurrent tapeout programs; track progress, manage risk, and report status to executive leadership
  • Drive continuous improvement in verification infrastructure including regression frameworks, CI/CD integration, coverage analytics, and productivity tooling
  • Ensure IP compliance with relevant industry standards including IEEE 802.3, UCIe, and emerging D2D interconnect specifications
  • Evaluate, integrate, and manage 3rd party VIPs and AMS verification IP; coordinate feature/bug tracking and vendor relationships
  • Oversee development of DPI-based firmware co-simulation environments and system-level verification strategies for PHY bring-up and validation
  • Oversee GLS environments for functional, timing, and power-aware simulations; drive signoff quality for tapeout readiness
Qualifications:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 15+ years of experience in design verification of high-speed serial interfaces, PHYs, and controller IPs, with at least 5 years in a people-management or leadership role
  • Deep expertise in SystemVerilog/UVM methodology, constrained-random verification, assertion-based verification, and formal verification techniques
  • Demonstrated experience with AMS verification methodologies including real-number modeling (RNM), Verilog-AMS, SVAMS co-simulation, and mixed-signal behavioral modeling
  • Strong working knowledge of link layer protocols, PCS architectures (including FEC — RS-FEC, KP4, KR4), Ethernet 802.3 clauses for 100G/200G/400G/800G, and die-to-die interconnect standards such as UCIe
  • Proven ability to drive verification innovation including automation, AI/ML-assisted verification, and scalable methodologies that improve team productivity and product quality
  • Hands-on experience verifying mixed-signal IPs (PLLs, CDRs, SerDes analog front-ends, DLLs) and integrating analog models into digital verification environments
  • Track record of successfully building and scaling verification teams in startup or high-growth environments with multiple concurrent tapeouts
  • Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect verification a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.