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Cpu Rtl Design Engineer Jobs (NOW HIRING)

Engineering Group, Engineering Group > CPU Engineering General Summary: We are seeking a highly ... You'll work closely with CPU design teams to support RTL development, triage issues, and enhance ...

Expertise in CPU processor designs in one or more of the following areas: instruction fetch and ... Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL. Experience with Scala ...

RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

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Cpu Rtl Design Engineer information

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$40.5K

$88.2K

$158.5K

How much do cpu rtl design engineer jobs pay per year?

As of Jul 10, 2026, the average yearly pay for cpu rtl design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
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What cities are hiring for Cpu Rtl Design Engineer jobs? Cities with the most Cpu Rtl Design Engineer job openings:
What states have the most Cpu Rtl Design Engineer jobs? States with the most job openings for Cpu Rtl Design Engineer jobs include:
Staff RTL Design Engineer - CPU LS/PF/MMU

Staff RTL Design Engineer - CPU LS/PF/MMU

SiFive

Austin, TX • On-site

$178K - $218K/yr

Full-time

Medical, Retirement, PTO

Posted 11 days ago


Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive's phenomenal success and to see why we have won theGSA's prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsiteandGlassdoorpages.

Job Description:

The Role

As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-standard RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

  • Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.

  • Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.

  • Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.

  • Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.

  • Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.

  • Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Requirements

  • BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.

  • 3+ years of design experience.

  • Academic or professional experience with CPU RTL design.

  • Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.

  • Strong software engineering skills/background, including:

    • Object-oriented, aspect-oriented, and particularly functional programming

    • Test-driven development, particularly ability to write adaptive unit tests

  • Attention to detail and a focus on high-quality design. Good verification principles, SVA, and coverage.

  • Ability to work well with others and share the belief that engineering is teamwork.

Nice-to-haves

  • Experience with Scala/Chisel, Bluespec, or some other language/DSL for generating configurable hardware via software.

  • Knowledge of RISC-V instruction set architecture.

  • Expertise in out-of-order processor micro-architecture, design, and verification in one or more of the following areas: load-store unit, coherent caches, cache prefetching, virtual memory MMU/TLBs.

  • Familiarity with Git/Github, Jira, Confluence.

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

$178,848.00-$218,592.00

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

United States of America

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.