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Cpu Rtl Design Engineer Jobs in Utah (NOW HIRING)

Wipro Limited

Design Verification Engineer

Santa Clara, UT · On-site

$60K - $148.50K/yr

Design Verification Engineer City: Santa Clara State/Province: California Posting Start Date: 5/20 ... RTL designers to resolve issues Execute regression runs, analyze results, and contribute to ...

Wipro Limited

L6 PDE FA Engineer

Santa Clara, UT · On-site

$45K - $110K/yr

L6 PDE FA Engineer City: Santa Clara State/Province: California Posting Start Date: 5/4/26 Wipro ... design, NPI, and volume production * Review schematics, layout, and component selections (CPU, GPU ...

EndoSec LLC

FPGA Engineer

Salt Lake City, UT

$125.80K - $161.60K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Wipro Limited

L6 PDE (CONTRACT)

Santa Clara, UT · On-site

$45K - $121K/yr

... Engineering * Drive CM/ODM execution for NVIDIA server products across design, NPI, and volume production * Review schematics, layout, and component selections (CPU, GPU, DDR, PCIe, VRM, NIC, storage)

EndoSec LLC

FPGA Engineer

Salt Lake City, UT · On-site

$125.80K - $161.60K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Avetta, LLC

Senior DevOps Engineer I

Lehi, UT · On-site

$122K - $156.80K/yr

Work with RESTful architecture design and HTTP protocol. Be able to respond and troubleshoot ... measuring CPU, Memory, I/O, Disk, and process threads dumps; managing and integrating and ...

Avetta, LLC

Senior DevOps Engineer I

Lehi, UT

$122K - $156.80K/yr

Work with RESTful architecture design and HTTP protocol. Be able to respond and troubleshoot ... measuring CPU, Memory, I/O, Disk, and process threads dumps; managing and integrating and ...

Avetta

Senior DevOps Engineer I

Lehi, UT · On-site

$122K - $156.80K/yr

Work with RESTful architecture design and HTTP protocol. Be able to respond and troubleshoot ... measuring CPU, Memory, I/O, Disk, and process threads dumps; managing and integrating and ...

Zions Bancorporation

Software Engineer

Midvale, UT · On-site

Design secure Apigee proxies/policies (OAuth2/OIDC, JWT, quotas, routing). * Build resilient Java ... React + Redux; Jest/RTL. * Docker & Kubernetes). * CI/CD, Git, and secure SDLC. * Requires a ...

University of Utah

Network Engineers

Salt Lake City, UT · On-site

$65K - $95K/yr

... 000+ CPU cores, 1,000+ GPU resources, and 50PB+ of storage. CHPC seeks a network engineer to ... This work involves all aspects of network design, engineering, and administration. Physical work ...

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Cpu Rtl Design Engineer information

See Utah salary details

$36.9K

$80.2K

$144.3K

How much do cpu rtl design engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for cpu rtl design engineer in Utah is $80,249.00, according to ZipRecruiter salary data. Most workers in this role earn between $61,900.00 and $89,700.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

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Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Utah as of May 2026, with employment types broken down into 1% As Needed, 3% Full Time, 64% Part Time, and 32% Contract. Highlights an 95% Physical, and 5% Remote job distribution, with an average salary of $80,249 per year, or $38.6 per hour.

Direct-Hire -- Principal Digital ASIC Design Engineer -- Clearfield, UT (Onsite)

TWC Global Services LLC

Clearfield, UT • On-site

$126.80K/yr

Full-time

Posted 2 days ago

Job description

Job Title: Principal Digital ASIC Design Engineer

Location: Clearfield, UT (Onsite)

Job Type: Direct-Hire Position

Industry(ies) - Aerospace / Defense

Primary Skills - Digital ASIC design

Secondary Skills - Digital IC design

Occupational Categories - Engineering/ Manufacturing/ Production/ Operations

Job Description:

We are seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. 

  • As a Principal Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies.
  • You will be responsible for implementing designs from RTL through synthesis.
  • You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in different application areas.

Duties/Responsibilities:

  • Drive solutions to complex problems with limited direction contribute to requirements development, propose ways forward, and adapt appropriately to changes in requirements.
  • Independently performs complex ASIC architectures and designs.
  • Provide insight and suggest design modifications based on simulation results.
  • Identify program/system-level technical risks and develop and execute mitigation strategies.
  • Manage a task with multiple engineers and effectively communicate status to project leadership and customers.
  • Mentor less experienced engineers and provide thoughtful, constructive feedback.
  • Perform other duties as assigned.

Skills/Abilities:

  • Proficiency in ASIC design, microprocessor programming or embedded computing.
  • Understanding of ASIC design and general computer architecture.
  • Ability to write detailed design specifications.
  • Computer programming and coding abilities.
  • Excellent verbal and written communication skills.
  • Excellent mathematical skills.
  • Excellent organizational skills and attention to detail.
  • Excellent time management skills with the proven ability to meet deadlines.
  • Strong analytical and problem-solving skills.
  • Ability to prioritize tasks.
  • Thorough understanding of engineering theories and procedures.

Education:

  • Requires bachelor's degree in engineering, or related field. Master’s degree preferred.

Experience:

  • Requires 7-10 years of experience with a bachelor's degree.

Additional Job Description:

  • Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys.
  • Be fluent in System Verilog, Verilog or VHDL and familiar with LINT, simulation and synthesis.
  • Familiarity with architectures for secure systems design, e.g., cryptographic encoders / decoders or tagged processor architectures is a plus.
  • Demonstrated experience with successful tape-outs at advanced nodes is desired. Experience leading and managing design teams is also a plus.
  • Applicants selected for this position will be required to obtain and maintain a U.S. Security Clearance.