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Cpu Rtl Design Engineer Jobs in Orem, UT (NOW HIRING)

Avetta, LLC

Senior DevOps Engineer I

Lehi, UT · On-site

$122K - $156.80K/yr

Work with RESTful architecture design and HTTP protocol. Be able to respond and troubleshoot ... measuring CPU, Memory, I/O, Disk, and process threads dumps; managing and integrating and ...

Avetta, LLC

Senior DevOps Engineer I

Lehi, UT · On-site

$122K - $156.80K/yr

Work with RESTful architecture design and HTTP protocol. Be able to respond and troubleshoot ... measuring CPU, Memory, I/O, Disk, and process threads dumps; managing and integrating and ...

Zions Bancorporation

Software Engineer

Midvale, UT · On-site

Design secure Apigee proxies/policies (OAuth2/OIDC, JWT, quotas, routing). * Build resilient Java ... React + Redux; Jest/RTL. * Docker & Kubernetes). * CI/CD, Git, and secure SDLC. * Requires a ...

Novarad Corporation

Database Administrator

Provo, UT

Proactively monitor and tune database performance, addressing high CPU usage, memory bottlenecks ... Partner with software engineers during the development lifecycle to design efficient schemas ans ...

Novarad Corporation

Be Seen First

Database Administrator

Provo, UT · On-site

... CPU usage, memory bottlenecks, and I/O contention • Analyze query execution plans, identify ... engineers during the development lifecycle to design efficient schemas ans write optimized SQL ...

Novarad Corporation

Database Administrator

Provo, UT · On-site

... CPU usage, memory bottlenecks, and I/O contention • Analyze query execution plans, identify ... engineers during the development lifecycle to design efficient schemas ans write optimized SQL ...

Novarad

Database Administrator

Provo, UT · On-site

... CPU usage, memory bottlenecks, and I/O contention • Analyze query execution plans, identify ... engineers during the development lifecycle to design efficient schemas ans write optimized SQL ...

People also search for

All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Orem, UT

Cpu Rtl Design Engineer information

See Orem, UT salary details

$35.2K

$76.6K

$137.8K

How much do cpu rtl design engineer jobs pay per year?

As of May 29, 2026, the average yearly pay for cpu rtl design engineer in Orem, UT is $76,635.00, according to ZipRecruiter salary data. Most workers in this role earn between $59,100.00 and $85,600.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Orem, UT? For Cpu Rtl Design Engineer jobs in Orem, UT, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Orem, UT look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Orem, UT are:
Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Orem, UT as of May 2026, with employment types broken down into 1% As Needed, 8% Full Time, 62% Part Time, and 29% Contract. Highlights an 95% Physical, and 5% Remote job distribution, with an average salary of $76,635 per year, or $36.8 per hour.
Senior DevOps Engineer I

Senior DevOps Engineer I

Avetta, LLC

Lehi, UT • On-site

$122K - $156.80K/yr

Full-time

Posted 11 days ago

Job description

Job ID #7190
JOB TITLE: Sr. DevOps Engineer I
LOCATION: 3300 N. Triumph Blvd., Suite 800, Lehi, UT 84043
(With Telecommuting Benefits)
RESPONSIBILITIES:
Automate reproducible infrastructure to maintain predictably and security. Support infrastructure for
both production and development systems. Provide Continuous Integration and Deployment
Infrastructure, utilizing Git, and CI tools like Github Actions, Jenkins to maintain continuous builds &
deployments. Ability to maintain hundreds of servers through predictable and repeatable automation
with provisioning and configuration management tools like SaltStack, Terraform, Packer. Strong
knowledge in Linux/Unix administration. Maintain enterprise grade backups, well tested restore and
understanding of data encryption. Work with networking tools like DNS, NAT, Internet Gateways, stateless
applications to maintain an effective microservices architecture. Work with RESTful architecture design
and HTTP protocol. Be able to respond and troubleshoot Production outages 24/7 for a global SaaS
platform. Manage NOC responsibilities and delegate and communicate with teams to reduce MTTR.
Automate 24/7 monitors and checks to provide real-time insight into Production systems. Be proficient in
load balancers, microservices architecture, and designing and maintaining highly available systems.
Automate disaster recovery systems. Manage and identify cost-optimization managing FinOps. Develop
new ways of optimizing recyclable and scalable infrastructure including but not limited to containers,
Kubernetes, serverless technologies. Innovate and improve infrastructure and automation as the DevOps
space continues to evolve. Display creativity in finding ways to increase security while maintaining agility.
Lead in innovation and new and relevant technologies help the business continue to scale. Collaborate in
making system-wide architecture improvements with system architects. Work with Saltstack,
GlusterFS/FsX, AWS, ELK or other centralized logging, Load-Balancers: HAProxy or f5, Bash / Python 2.7+,
Docker, MongoDB & SQL, NewRelic.
JOB REQUIREMENTS:
Minimum Education: Bachelor's Degree in Computer Science, Mechanical Engineering or related field.
Minimum Experience: 5 years of experience in troubleshooting modern container and networking
technologies (Docker, Kubernetes, HAProxy, ELB); monitoring performance of entire networking stack,
using distribute tracing, profile and other networking tools; profiling tools for measuring CPU, Memory,
I/O, Disk, and process threads dumps; managing and integrating and automating for alerting and
escalation (PagerDuty, Teams, Slack); and monitoring RESTful microservices architecture design basic
HTTP protocols.
Apply online at Careers Listing | Avetta. Must include job ID #7190 on the resume.
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