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Cpu Rtl Design Engineer Jobs in Oakland, CA (NOW HIRING)

Mythic

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Baidu USA

Senior RTL Design Engineer

Sunnyvale, CA · On-site

Expertise in CPU processor designs in one or more of the following areas: instruction fetch and ... Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL. Experience with Scala ...

Baidu USA

Senior RTL Design Engineer

Sunnyvale, CA · On-site

Requirements: • 8+ yrs of recent industry experience in high-performance, energy-efficient CPU ... RTL) design in Verilog, System Verilog, or VHDL. • Experience with Scala and/or Chisel is a plus ...

Mythic

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Mythic

RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Mythic

Senior RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...

Mythic

Senior RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...

Mythic

Senior RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...

Baidu USA

CPU Digital Design Engineer

Sunnyvale, CA · On-site

$159K/yr

A t least 3 years of CPU related Architect/RTL/Verification/Implementation design experience * K ... P hD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS. * 5 + years of ...

Baidu USA

CPU Digital Design Engineer

Sunnyvale, CA · On-site

$159K/yr

Minimum Qualifications: - Master Degree in Electrical Engineering, Computer Science or Computer Engineering. - At least 3 years of CPU related Architect/RTL/Verification/Implementation design ...

Etched

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both ...

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All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Oakland, CA

Cpu Rtl Design Engineer information

See Oakland, CA salary details

$46.5K

$101.2K

$182K

How much do cpu rtl design engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for cpu rtl design engineer in Oakland, CA is $101,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $78,100.00 and $113,100.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What job categories do people searching Cpu Rtl Design Engineer jobs in Oakland, CA look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Oakland, CA are:
What cities near Oakland, CA are hiring for Cpu Rtl Design Engineer jobs? Cities near Oakland, CA with the most Cpu Rtl Design Engineer job openings:
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Infographic showing various Cpu Rtl Design Engineer job openings in Oakland, CA as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $101,238 per year, or $48.7 per hour.

Senior CPU RTL Design Engineer

Google

Mountain View, CA • On-site

Full-time

Posted 15 days ago

Google rating

8.9

Company rating: 8.9 out of 10

Based on 102 frontline employees who took The Breakroom Quiz

40th of 242 rated software companies

Job description

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
  • Experience with RTL language (e.g. System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:
  • PhD in Electrical Engineering or Computer Science, or a related field.
  • Experience leading front-end design for modern processor components or AI accelerators.
  • Experience with ARM Instruction Set Architecture or CPU subsystems.
  • Experience with SoC design, architecture, and integration.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $237000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
  • Engage in developing CPU cache subsystems, focusing on RTL design and microarchitecture for future CPU generations.
  • Collaborate with performance, architecture, and software teams to evaluate trade-offs and suggest microarchitectural improvements that boost performance.
  • Deliver high-quality designs on time while articulating the advantages and disadvantages of various microarchitecture updates.
  • Partner with verification, power, and physical design teams to ensure designs meet area, power, and frequency targets.
  • Optimize cache unit design and coordinate with other design units within CPU subsystems to achieve excellent power, performance, and area.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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