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Cpu Rtl Design Engineer Jobs in La Jolla, CA (NOW HIRING)

Info Way Solutions

Staff Engineer

San Diego, CA · On-site

Design and optimize high-performance CPU/SoC blocks from microarchitecture through RTL and physical ... Mentor junior engineers and contribute to methodology and flow improvements. Required ...

New

Apple

RTL Design Engineer

San Diego, CA

$175K - $308K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

Apple Inc.

RTL Design Engineer

San Diego, CA · On-site

$122.70 - $214.30/hr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

Apple

RTL Design Engineer

San Diego, CA

$122K - $214K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

Apple

RTL Design Engineer

San Diego, CA · On-site

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

Apple

RTL Design Engineer

San Diego, CA · On-site

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

Mirafra Technology

RTL Design Engineer

San Diego, CA

... RTL design and test planning - Timing closure experience including timing constraints and PTSI. - Prior experience in digital and mixed signal circuit design for high speed PHYs - Hands-on experience ...

Qualcomm

Processor ASIC RTL Design Engineer

San Diego, CA · On-site

$127K - $190K/yr

RTL, processor, Verilog, System Verilog, logic design, digital design, processor integration, bus interface, cache. Minimum Qualifications: • Bachelor's degree in Electrical Engineering, Computer ...

CivicMinds, Inc.

RTL / Digital Design Engineer

San Diego, CA · On-site

$145K/yr

RTL/Digital design engineers will design and implementation of SoC, Peripherals, Graphics, Modem, Bus and Network-on-chip cores. These candidates will understand and work on all aspects of the VLSI ...

Apple

GPU RTL Design Engineer

San Diego, CA · On-site

Description As a GPU Design Engineer, you will be responsible for delivering high-quality, low ... Strong background in GPU, CPU, or SIMD architectures. Logic design, with expert knowledge of low ...

Apple

GPU RTL Design Engineer

San Diego, CA · On-site

Description As a GPU Design Engineer, you will be responsible for delivering high-quality, low ... Strong background in GPU, CPU, or SIMD architectures. Logic design, with expert knowledge of low ...

Apple

GPU RTL Design Engineer

San Diego, CA · On-site

$142K - $263K/yr

Description As a GPU Design Engineer, you will be responsible for delivering high-quality, low ... Strong background in GPU, CPU, or SIMD architectures. Logic design, with expert knowledge of low ...

Apple

GPU RTL Design Engineer

San Diego, CA

$142K - $263K/yr

Description As a GPU Design Engineer, you will be responsible for delivering high-quality, low ... Strong background in GPU, CPU, or SIMD architectures. Logic design, with expert knowledge of low ...

Apple

DDR Design Engineer

San Diego, CA · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Apple

DDR Design Engineer

San Diego, CA · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

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All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in La Jolla, CA

Cpu Rtl Design Engineer information

See La Jolla, CA salary details

$42.5K

$92.4K

$166.2K

How much do cpu rtl design engineer jobs pay per year?

As of Sep 5, 2026, the average yearly pay for cpu rtl design engineer in La Jolla, CA is $92,420.00, according to ZipRecruiter salary data. Most workers in this role earn between $71,300.00 and $103,300.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What job categories do people searching Cpu Rtl Design Engineer jobs in La Jolla, CA look for?

The top searched job categories for Cpu Rtl Design Engineer jobs in La Jolla, CA are:

What cities near La Jolla, CA are hiring for Cpu Rtl Design Engineer jobs?

Cities near La Jolla, CA with the most Cpu Rtl Design Engineer job openings:

Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in La Jolla, CA as of August 2026, with employment types broken down into 79% Full Time, 5% Part Time, and 16% Contract. Highlights an 90% In-person, 4% Hybrid, and 6% Remote job distribution, with an average salary of $92,420 per year, or $44.4 per hour.

Staff Engineer

Info Way Solutions

San Diego, CA • On-site

Other

Posted 2 days ago

New

Job description

Qualcomm-- San Diego, CA
 
 
Company: Qualcomm
Experience: 4–10 years
Location: San Diego, CA 
Job Summary
Qualcomm is seeking a highly skilled Staff Engineer with strong experience in CPU design, RTL development, and/or Physical Design (PD) to work on next-generation high-performance, low-power SoCs and CPU architectures.
The ideal candidate will have hands-on experience in ASIC/SoC development, strong understanding of CPU microarchitecture and digital design, and the ability to work across RTL, synthesis, physical implementation, timing, power, and area optimization. The engineer will collaborate closely with Architecture, RTL, Design Verification, Physical Design, DFT, CAD, Power, and Post-Silicon teams.
Key Responsibilities
  • Design and optimize high-performance CPU/SoC blocks from microarchitecture through RTL and physical implementation.
  • Develop, review, and refine Verilog/SystemVerilog RTL.
  • Participate in microarchitecture definition and design trade-offs targeting Power, Performance, and Area (PPA).
  • Work closely with Physical Design teams on synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff.
  • Analyze and resolve timing, congestion, power, area, and design-closure issues.
  • Support RTL-to-GDS implementation and identify RTL changes required for physical convergence.
  • Perform or support STA/MMMC analysis, constraint development, and timing optimization.
  • Collaborate with verification teams on functional verification, coverage, debugging, and design quality.
  • Work with DFT, CAD, and implementation teams to resolve complex design issues.
  • Develop automation and productivity solutions using Python, Tcl, Perl, or Shell.
  • Participate in design reviews and provide technical leadership on critical design problems.
  • Mentor junior engineers and contribute to methodology and flow improvements.
Required Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 4–10 years of experience in ASIC/SoC, CPU, RTL, or Physical Design.
  • Strong understanding of digital design and ASIC development flows.
  • Hands-on experience with Verilog/SystemVerilog.
  • Strong understanding of CPU/microprocessor architecture is highly preferred.
  • Experience with one or more of:
    • RTL design
    • Logic design
    • Synthesis
    • Physical Design
    • Static Timing Analysis
    • Timing closure
    • PPA optimization
    • SoC integration
  • Experience working in Linux/Unix environments.
  • Strong scripting/programming skills in Python, Tcl, Perl, or Shell.
  • Strong debugging, analytical, and problem-solving skills.
Preferred Qualifications
CPU / RTL
  • Experience with CPU pipeline architecture, including Fetch, Decode, Rename, Execute, Load/Store, Cache, MMU, or Branch Prediction.
  • Experience with out-of-order execution, memory hierarchy, or processor microarchitecture.
  • Strong RTL coding and microarchitecture implementation experience.
  • Knowledge of CDC, lint, synthesis, formal verification, and low-power design.
Physical Design
  • Experience with complete RTL-to-GDSII flow.
  • Floorplanning, power planning, placement, CTS, routing, and timing closure.
  • Experience with Cadence Innovus and/or Synopsys Fusion Compiler.
  • Experience with PrimeTime STA.
  • MMMC timing analysis and advanced-node implementation.
  • Experience with IR drop, EM, signal integrity, crosstalk, ECOs, and physical verification.
  • Knowledge of UPF and low-power implementation.

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