Description:
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Job Description: Digital Design (RTL) Engineer
Location: Santa Clara, CA
Remote work option allowed
Required:
Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog
Experience in developing micro architectural document from requirements specifications
Experience developing designs from scratch
Experience applying linting and other (QC) quality checking and basic verification of designs.
Experience supporting SoC designers in integration as needed
Strong communication and collaboration skills
Preferred:
-Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces.
- Candidate with design automation, scripting experience (Python) is preferrable
• Develop HW architecture from specification documents.
• Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low power design (UPF/CPF).
• Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
• Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
• Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
• Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
• Take ownership of tasks and drive tasks to closure.
Synopsys/Cadence EDA Tools (Priority: 1)
LEC (Priority: 2)
STA/Constraints (Priority: 2)
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details
- Global Grade : C
- Named Job Posting? (if Yes - needs to be approved by SCSC) : No
- Remote work possibility : (No Value)
- Global Role Family : 60239 (P) Cloud Infrastructure
- Global Technical Skills Family : 6246 (T) Network operate & administration Technologies
- Local Role Name : Digital Design (RTL) Engineer
- Local Skills : Julie Skidmore
- Languages Required: : English