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Remote System Verilog Jobs (NOW HIRING)

Redolent, Inc.

US_West | Network Design Engineer_L3

$102.40K - $140.20K/yr

Santa Clara, CA Remote work option allowed Required: Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural ...

iDirect GOVERNMENT

Senior FPGA Engineer

Herndon, VA · On-site +1

$133.70K - $171.70K/yr

This position is based out of our Herndon, VA location with the option of a remote work schedule ... Implementing and documenting FPGA designs using HDL (System Verilog, VHDL, etc.) * Supporting ...

Cornelis Networks

Senior ASIC Design Engineer

Austin, TX · On-site +1

... remote roles. Cornelis Networks is seeking talented Senior ASIC Design Engineers with deep ... Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing ...

Zortech Solutions

SOC Verification

New Marlborough, MA · Remote

$139.20K/yr

Remote 1. General verification expertise - * System Verilog * UVM working experience (In the current scenario not much on UVM, but heavily on "C") * Understanding of ARM processor based SOCs, AXI ...

Next Step Systems

FPGA Engineer - Work From Home

Chicago, IL · On-site +1

$133.90K - $172K/yr

... System Verilog. - Proficiency with a full simulator such as ModelSim. - Ability to transition ... Remote, Work From Home, Financial, Trading, Chicago Recruiters, Information Technology Jobs ...

QCi

$134.60K - $185.40K/yr

... well as remote sensing applications. Position Description: We are seeking a new FPGA Design ... Expertise in Verilog/System Verilog * Proficiency in RTL simulation (ModelSim,xSim etc.), and ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · On-site +1

... of whom are in remote locations. What we need to see: * A Bachelors or Masters Degree (or ... Expertise in Verilog, System Verilog or similar HDL. Proficient programming in Perl/Python (or ...

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How much do remote system verilog jobs pay per year?

As of May 29, 2026, the average yearly pay for remote system verilog in the United States is $127,215.00, according to ZipRecruiter salary data. Most workers in this role earn between $98,000.00 and $157,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Remote SystemVerilog Engineer, and why are they important?

To thrive as a Remote SystemVerilog Engineer, you need expertise in digital design, verification methodologies, and a solid understanding of hardware description languages, typically supported by a degree in electrical or computer engineering. Proficiency with tools such as ModelSim, Synopsys VCS, UVM, and source control systems like Git is standard in this role. Strong problem-solving skills, self-motivation, and effective remote communication are essential soft skills for success in a distributed team environment. These qualifications ensure efficient design and verification of complex hardware systems while maintaining productivity and collaboration remotely.

What are some common challenges faced by remote SystemVerilog engineers, and how can they be addressed?

Remote SystemVerilog engineers often encounter challenges such as collaborating effectively with hardware and verification teams across different locations, managing access to simulation tools and proprietary code, and ensuring clear communication on specification changes. To address these, it's important to establish reliable remote access solutions, use collaborative platforms like version control systems, and schedule regular virtual meetings to align on project goals and updates. Proactive communication and well-documented code reviews also help maintain workflow efficiency and integration with the broader engineering team.

What are Remote SystemVerilog jobs?

Remote SystemVerilog jobs involve working with the SystemVerilog hardware description and verification language from a remote location, such as your home or another offsite environment. Professionals in these roles typically design, model, and verify digital circuits and systems, collaborating with engineering teams virtually. These jobs require strong knowledge of SystemVerilog, digital design principles, and often involve using simulation tools and version control systems to contribute to hardware development projects.

What is the difference between Remote System Verilog vs Remote FPGA Engineer?

AspectRemote System VerilogRemote FPGA Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering, Verilog/SystemVerilog certificationsBachelor's in Electrical Engineering, FPGA design certifications, Verilog/SystemVerilog knowledge
Work EnvironmentDesign verification, simulation, and hardware description in a remote settingFPGA development, implementation, and testing remotely
Industry UsageSemiconductor, electronics, ASIC/FPGA design companiesEmbedded systems, telecommunications, aerospace, and defense sectors

Remote System Verilog and Remote FPGA Engineer roles share a focus on hardware description languages and often require similar technical credentials. However, Remote System Verilog primarily involves verification and simulation tasks, while Remote FPGA Engineers focus on designing and implementing FPGA hardware. Both roles are common in electronics and semiconductor industries, often offered remotely to skilled engineers.

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Remote System Verilog jobs near you

Design Verification Engineer - Remote

Futran Tech Solutions Pvt. Ltd.

Remote

$139.20K - $169.90K/yr

Full-time

Posted 15 days ago

Job description

Role - Design Verification Engineer
Location: Remote (must be aligned with PST time zone / willing to work PST hours)
Contract Term: Contract
Job Description:
We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build System Verilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write System Verilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.

Qualifications
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with a scripting language (e.g. Python, Perl, TCL) and revision control system (e.g. Git).

Nice to Have
  • Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
  • Familiarity with developing and integrating reference models.
  • Understanding of RTL design flows and some industry standard interfaces (e.g. APB/AHB/AXI).
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus.

Apply