... System Verilog and microarchitecture. * 4 years of experience in leading IP/SoC design teams ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
... System Verilog and microarchitecture. * 4 years of experience in leading IP/SoC design teams ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$126K - $162K/yr
PTO
... using System Verilog - Verification utilizing emulation platforms, such as Veloce Benefit selection, customer contractual specifications, relevant work experience, skills, competencies ...
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$126K - $162K/yr
PTO
... using System Verilog - Verification utilizing emulation platforms, such as Veloce Benefit selection, customer contractual specifications, relevant work experience, skills, competencies ...
Senior FPGA Design and Verification Engineer with Security Clearance
Tucson, AZ · On-site
$118K - $162K/yr
PTO
... using System Verilog - Verification utilizing emulation platforms, such as Veloce Benefit selection, customer contractual specifications, relevant work experience, skills, competencies ...
Senior FPGA Design and Verification Engineer with Security Clearance
Tucson, AZ · On-site
$118K - $162K/yr
PTO
... using System Verilog - Verification utilizing emulation platforms, such as Veloce Benefit selection, customer contractual specifications, relevant work experience, skills, competencies ...
VP, System Engineering
Irvine, CA · On-site
$193K - $249K/yr
Responsible for timely deliveries of all contractual Obligations of the Systems Division. * Handles ... OrCAD, Altium, PSpice, and Verilog, PCB design and testing * Solid time management skills and ...
VP, System Engineering
Irvine, CA · On-site
$193K - $249K/yr
Responsible for timely deliveries of all contractual Obligations of the Systems Division. * Handles ... OrCAD, Altium, PSpice, and Verilog, PCB design and testing * Solid time management skills and ...
Silicon Design Verification Manager
Austin, TX · On-site
$134K - $164K/yr
Object Oriented design verification coding (System Verilog or C ); Testbench architecture design ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Silicon Design Verification Manager
Austin, TX · On-site
$134K - $164K/yr
Object Oriented design verification coding (System Verilog or C ); Testbench architecture design ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
System Verilog) and related design processes (e.g., Lint, UPF). Preferred qualifications: * PhD in ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
System Verilog) and related design processes (e.g., Lint, UPF). Preferred qualifications: * PhD in ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Staff FPGA Engineer
Reston, VA · On-site
$150K - $195K/yr
... VHDL and/or Verilog * Experience in SoC hardware bring-up, preferably on ARM-based systems ... contractual requirements which may cause an offer to fall outside of this range.
Staff FPGA Engineer
Reston, VA · On-site
$150K - $195K/yr
... VHDL and/or Verilog * Experience in SoC hardware bring-up, preferably on ARM-based systems ... contractual requirements which may cause an offer to fall outside of this range.
Staff FPGA Engineer
Reston, VA · On-site
$150K - $195K/yr
... VHDL and/or Verilog * Experience in SoC hardware bring-up, preferably on ARM-based systems ... include contractual requirements which may cause an offer to fall outside of this range.
Staff FPGA Engineer
Reston, VA · On-site
$150K - $195K/yr
... VHDL and/or Verilog * Experience in SoC hardware bring-up, preferably on ARM-based systems ... include contractual requirements which may cause an offer to fall outside of this range.
Staff FPGA Engineer with Security Clearance
Reston, VA · On-site
$150K - $195K/yr
... VHDL and/or Verilog * Experience in SoC hardware bring-up, preferably on ARM-based systems ... contractual requirements which may cause an offer to fall outside of this range.
Staff FPGA Engineer with Security Clearance
Reston, VA · On-site
$150K - $195K/yr
... VHDL and/or Verilog * Experience in SoC hardware bring-up, preferably on ARM-based systems ... contractual requirements which may cause an offer to fall outside of this range.
VP Systems Engineering
Irvine, CA · On-site
$193K - $249K/yr
Actively participates in design reviews and approves system design and configuration for all ... Responsible for timely deliveries of all contractual Obligations of the Systems Division. Handles ...
VP Systems Engineering
Irvine, CA · On-site
$193K - $249K/yr
Actively participates in design reviews and approves system design and configuration for all ... Responsible for timely deliveries of all contractual Obligations of the Systems Division. Handles ...
Embedded Systems Design Engineer
Laurel, MD · On-site
Medical
Dental
Vision
Life
Retirement
PTO
You 'll be joining our hardworking team of system engineers, algorithm developers, FPGA and ... Have experience with VHDL, Verilog, or other FPGA development languages. * Have experience in ...
Embedded Systems Design Engineer
Laurel, MD · On-site
Medical
Dental
Vision
Life
Retirement
PTO
You 'll be joining our hardworking team of system engineers, algorithm developers, FPGA and ... Have experience with VHDL, Verilog, or other FPGA development languages. * Have experience in ...
Embedded Systems Design Engineer with Security Clearance
Laurel, MD · On-site
Medical
Dental
Vision
Life
Retirement
PTO
You 'll be joining our hardworking team of system engineers, algorithm developers, FPGA and ... Have experience with VHDL, Verilog, or other FPGA development languages. * Have experience in ...
Embedded Systems Design Engineer with Security Clearance
Laurel, MD · On-site
Medical
Dental
Vision
Life
Retirement
PTO
You 'll be joining our hardworking team of system engineers, algorithm developers, FPGA and ... Have experience with VHDL, Verilog, or other FPGA development languages. * Have experience in ...
Reverse Engineer for RF Systems
Laurel, MD · On-site
Medical
Dental
Vision
Life
Retirement
PTO
Have experience with VHDL, Verilog, or other FPGA development languages * Have developed novel ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Reverse Engineer for RF Systems
Laurel, MD · On-site
Medical
Dental
Vision
Life
Retirement
PTO
Have experience with VHDL, Verilog, or other FPGA development languages * Have developed novel ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Reverse Engineer for RF Systems with Security Clearance
Laurel, MD · On-site
Medical
Dental
Vision
Life
Retirement
PTO
Have experience with VHDL, Verilog, or other FPGA development languages * Have developed novel ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Reverse Engineer for RF Systems with Security Clearance
Laurel, MD · On-site
Medical
Dental
Vision
Life
Retirement
PTO
Have experience with VHDL, Verilog, or other FPGA development languages * Have developed novel ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
FPGA Engineer
Tewksbury, MA · On-site
$80K - $190K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Translate system-level requirements into detailed FPGA design requirements * Code and implement ... Demonstrated experience with VHDL or Verilog * Experience with FPGA platforms - AMD/Xilinx, Intel ...
FPGA Engineer
Tewksbury, MA · On-site
$80K - $190K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Translate system-level requirements into detailed FPGA design requirements * Code and implement ... Demonstrated experience with VHDL or Verilog * Experience with FPGA platforms - AMD/Xilinx, Intel ...
FPGA Engineer
Tewksbury, MA · On-site
$80K - $190K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Translate system-level requirements into detailed FPGA design requirements * Code and implement ... Demonstrated experience with VHDL or Verilog * Experience with FPGA platforms - AMD/Xilinx, Intel ...
FPGA Engineer
Tewksbury, MA · On-site
$80K - $190K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Translate system-level requirements into detailed FPGA design requirements * Code and implement ... Demonstrated experience with VHDL or Verilog * Experience with FPGA platforms - AMD/Xilinx, Intel ...
FPGA Engineer
$80K - $190K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Translate system-level requirements into detailed FPGA design requirements * Code and implement ... Demonstrated experience with VHDL or Verilog * Experience with FPGA platforms - AMD/Xilinx, Intel ...
FPGA Engineer
$80K - $190K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Translate system-level requirements into detailed FPGA design requirements * Code and implement ... Demonstrated experience with VHDL or Verilog * Experience with FPGA platforms - AMD/Xilinx, Intel ...
FPGA Engineer with Security Clearance
Tewksbury, MA · On-site
$80K - $190K/yr
Medical
Dental
Vision
Life
Retirement
PTO
... system requirements. This position requires an Active DoD Secret Security Clearance and is based on ... Verilog • Experience with FPGA platforms - AMD/Xilinx, Intel/Altera, or Microchip (Altera ...
FPGA Engineer with Security Clearance
Tewksbury, MA · On-site
$80K - $190K/yr
Medical
Dental
Vision
Life
Retirement
PTO
... system requirements. This position requires an Active DoD Secret Security Clearance and is based on ... Verilog • Experience with FPGA platforms - AMD/Xilinx, Intel/Altera, or Microchip (Altera ...
ASIC Design Verification Engineer, Google Cloud
Sunnyvale, CA · On-site
$116 - $166/hr
... systems. As an Application‑Specific Integrated Circuit (ASIC) Design Verification Engineer, you ... Experience with SystemVerilog/Verilog. Preferred Qualifications * Master's degree or PhD in ...
ASIC Design Verification Engineer, Google Cloud
Sunnyvale, CA · On-site
$116 - $166/hr
... systems. As an Application‑Specific Integrated Circuit (ASIC) Design Verification Engineer, you ... Experience with SystemVerilog/Verilog. Preferred Qualifications * Master's degree or PhD in ...
Experience in RTL design using Verilog or SystemVerilog. * Experience writing scripts or developing ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Posted today
Experience in RTL design using Verilog or SystemVerilog. * Experience writing scripts or developing ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Posted today
Contractual System Verilog information
See salary details
$53.5K - $63.8K
2% of jobs
$63.8K - $74.1K
4% of jobs
$74.1K - $84.5K
7% of jobs
$84.5K - $94.8K
9% of jobs
$97.6K is the 25th percentile. Wages below this are outliers.
$94.8K - $105.1K
10% of jobs
$105.1K - $115.4K
7% of jobs
$115.4K - $125.7K
10% of jobs
The median wage is $127.4K / yr.
$125.7K - $136K
6% of jobs
$136K - $146.4K
3% of jobs
$156.4K is the 75th percentile. Wages above this are outliers.
$146.4K - $156.7K
17% of jobs
$156.7K - $167K
24% of jobs
$53.5K
$127.2K
$167K
How much do contractual system verilog jobs pay per year?
As of Aug 14, 2026, the average yearly pay for contractual system verilog in the United States is $127,215.00, according to ZipRecruiter salary data. Most workers in this role earn between $98,000.00 and $157,000.00 per year, depending on experience, location, and employer.
What is the difference between Contractual System Verilog vs FPGA Design Engineer?
| Aspect | Contractual System Verilog | FPGA Design Engineer |
|---|---|---|
| Required Credentials | Verilog/SystemVerilog certifications, FPGA knowledge | Verilog/SystemVerilog, FPGA design certifications |
| Work Environment | Contract-based projects, design verification, simulation | Full-time or contract, FPGA development, hardware design |
| Employer & Industry Usage | Semiconductor, electronics, contract firms | Electronics, telecommunications, aerospace |
Contractual System Verilog professionals focus on verification and simulation tasks within contract roles, while FPGA Design Engineers are involved in hardware development and implementation. Both roles require Verilog/SystemVerilog skills but differ in their primary responsibilities and work settings.
More about Contractual System Verilog jobs
What cities are hiring for Contractual System Verilog jobs?
Cities with the most Contractual System Verilog job openings:
What are the most commonly searched types of System Verilog jobs?
The most popular types of System Verilog jobs are:
What states have the most Contractual System Verilog jobs?
States with the most job openings for Contractual System Verilog jobs include:
What job categories do people searching Contractual System Verilog jobs look for?
The top searched job categories for Contractual System Verilog jobs are:
Google rating
8.8
Based on 103 frontline employees who took The Breakroom Quiz
49th of 244 rated software companies
Job description
info_outline
X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.
Minimum qualifications:
Preferred qualifications:
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
- 4 years of experience in leading IP/SoC design teams.
- Experience with ARM-based SoCs, interconnects, and ASIC methodology.
Preferred qualifications:
- Master's degree in Electrical/Computer Engineering, or a related field.
- 10 years of experience with IP design for Complex IPs in Machine learning, Neural Processors, Multimedia or GPUs.
- Experience with methodologies for low power estimation, timing closure, and synthesis.
- Experience leading technical teams.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
- Contribute to Machine Learning IPs for Google Silicon SoCs.
- Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
- Drive RTL development, debug functional/performance simulations.
- Meet schedule commitments and provide strong support to customers.
- Participate in synthesis, timing/power estimation, and Field-programmable Gate Array (FPGA)/silicon bring-up.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
About Google
Sourced by ZipRecruiter
Industry
Software development and technology, communication and media
Company size
10,000+ Employees
Headquarters location
Mountain View, CA, US