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Cpu Rtl Design Engineer Jobs in South Carolina (NOW HIRING)

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

Tenstorrent

Chiplet Design Architect

North, SC · On-site +1

$100K - $500K/yr

D. in Computer Engineering, Electrical Engineering, Computer Science, or a related field. * 10+ years of experience in SoC, CPU, or chiplet architecture for high-performance computing or server-class ...

Tenstorrent

Memory Architect

North, SC · On-site +1

$100K - $500K/yr

... CPU, fabric, security, power, reliability, debug, system design, and scale-out. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation ...

Keysight Technologies, Inc.

Senior FPGA Engineer

Salters, SC · On-site

$133K - $172K/yr

Work with software engineers to define FPGA-CPU/SoC interfaces. * Develop documentation and participate in design reviews. * Support bring-up, debugging, and validation in the lab using oscilloscopes ...

AERONIX INC

Embedded Software Engineer

Greenville, SC · On-site

$90K - $125K/yr

... Engineer to design, develop, and integrate software for embedded systems with an emphasis on ... Develop software for both RTOS based systems and bare metal CPU environments without typical ...

Apolis

Wintel Lead (Dynatrace)

Fort Mill, SC · On-site

... CPU ready analysis, memory ballooning checks, and datastore optimization. • Troubleshoot host isolation, PSOD, VM performance issues, and storage latency. • Design VM templates, VM hardware ...

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Cpu Rtl Design Engineer information

See South Carolina salary details

$37.6K

$81.8K

$147.1K

How much do cpu rtl design engineer jobs pay per year?

As of Jul 31, 2026, the average yearly pay for cpu rtl design engineer in South Carolina is $81,799.00, according to ZipRecruiter salary data. Most workers in this role earn between $63,100.00 and $91,400.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
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Cpu Rtl Design Engineer jobs near you

Senior FPGA Design Engineer

AERONIX INC

Greenville, SC • On-site

$145K - $175K/yr

Full-time

Posted 8 days ago

Job description


Job Title: Senior FPGA Engineer
Department: Engineering
Reports To: Functional Team Lead / Program Manager
FLSA Status: Exempt / Full-time

Salary Range: $145k - $175k Annually

DoD Secret clearance (or higher) REQUIRED.


ROLE

We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop the architecture, implementation, and verification of complex, high-speed FPGA solutions. The ideal candidate will have deep expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5, along with strong skills in RTL design (VHDL/Verilog/ SystemVerilog), timing closure, and signal integrity. Experience with Cryptography, DSP and RF applications is strong plus. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.

RESPONSIBILITIES

  • Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.
  • Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.
  • Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure.
  • Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.
  • Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.
  • Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.
  • Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

REQUIRED SKILLS

  • Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
  • Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.
  • Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, ModelSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
  • Proficiency of FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
  • Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
  • Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422).
  • Experience with System-on-Chip technologies.

PREFERRED SKILLS

  • Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero).
  • Familiarity with Universal Verification Methodology (UVM).
  • Familiarity with Microsemi Libero and Lattus Diamond.
  • Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation.
  • Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers.
  • Support JTAG Boundary scan design and testing
  • Experience with Cryptography, Digital Signal Processing and RF Applications
  • MATLAB modeling
  • Strong oral and written communication skills, with ability to document and present technical work clearly.
  • Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).
  • Familiarity with Manufacturing processes, and Electronic Stress Screening.
  • Understanding of formal verification processes and compliance standards.

QUALIFICATIONS

  • Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field.
  • Minimum 10 years of relevant experience in FPGA design.
  • Excellent written and verbal communication skills.
  • Ability to work in a collaborative team environment.
  • DoD Secret clearance (or higher) REQUIRED.
  • Position located in Melbourne, FL or Greenville, SC (not remote).