ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon validation and software development * Map ASIC RTL to FGPA while minimizing code base differences * Create ...
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ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon validation and software development * Map ASIC RTL to FGPA while minimizing code base differences * Create ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon validation and software development * Map ASIC RTL to FGPA while minimizing code base differences * Create ...
San Jose, CA · On-site
$160K - $192K/yr
Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...
San Jose, CA · On-site
$160K - $192K/yr
Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...
San Jose, CA · On-site
... in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC ...
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San Jose, CA · On-site
... in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC ...
San Jose, CA · On-site
$180K - $223K/yr
Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using ...
San Jose, CA · On-site
$180K - $223K/yr
Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using ...
$170K - $223K/yr
Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using ...
$170K - $223K/yr
Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using ...
San Jose, CA · On-site
$180K - $223K/yr
Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using ...
San Jose, CA · On-site
$180K - $223K/yr
Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using ...
$194K/yr
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification) Description: Should have 2-5 years of experience in FPGA/ASIC ...
$194K/yr
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification) Description: Should have 2-5 years of experience in FPGA/ASIC ...
We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity ...
We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity ...
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Williston, VT · On-site +1
$100K - $165K/yr
We are presently seeking an experienced Full-Time ASIC Logic Design Engineer to help accelerate the pace of innovation with our customers. Can you see yourself collaborating with a dynamic team in a ...
Williston, VT · On-site +1
$100K - $165K/yr
We are presently seeking an experienced Full-Time ASIC Logic Design Engineer to help accelerate the pace of innovation with our customers. Can you see yourself collaborating with a dynamic team in a ...
Waukesha, WI · On-site
$40 - $50/hr
The successful candidate will interface with ASIC simulation & design teams, and Hardware Subsystem teams to help deliver mixed-signal and digital ASIC design solutions. Essential Responsibilities ...
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Waukesha, WI · On-site
$40 - $50/hr
The successful candidate will interface with ASIC simulation & design teams, and Hardware Subsystem teams to help deliver mixed-signal and digital ASIC design solutions. Essential Responsibilities ...
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Irvine, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will ...
Irvine, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will ...
$170K - $223K/yr
Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using ...
$170K - $223K/yr
Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using ...
We are seeking a highly skilled ASIC Architect with strong experience in architecture definition, logic design, synthesis, and system-level evaluation. The ideal candidate will assist with ...
We are seeking a highly skilled ASIC Architect with strong experience in architecture definition, logic design, synthesis, and system-level evaluation. The ideal candidate will assist with ...
Batavia, NY · Hybrid
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
Batavia, NY · Hybrid
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
We are seeking a highly skilled ASIC Architect with strong experience in architecture definition, logic design, synthesis, and systemlevel evaluation. The ideal candidate will assist with ...
We are seeking a highly skilled ASIC Architect with strong experience in architecture definition, logic design, synthesis, and systemlevel evaluation. The ideal candidate will assist with ...
San Jose, CA · On-site
$165K - $241K/yr
Experience with ASIC design flows including simulation, synthesis, and static timing analysis. * Experience with debug and problem-solving skills. Preferred Qualifications * Experience with data ...
San Jose, CA · On-site
$165K - $241K/yr
Experience with ASIC design flows including simulation, synthesis, and static timing analysis. * Experience with debug and problem-solving skills. Preferred Qualifications * Experience with data ...
Batavia, IL · On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
Batavia, IL · On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
Irvine, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will ...
Irvine, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will ...
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
| Aspect | Asic Design | FPGA Design |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; knowledge of VLSI design | Similar credentials; often requires knowledge of FPGA programming languages like VHDL/Verilog |
| Work Environment | Designing custom chips in semiconductor labs or design houses | Implementing and testing designs on FPGA boards in labs or development environments |
| Industry Usage | Used in high-volume, performance-critical applications like smartphones, servers | Used for prototyping, testing, and low to medium volume applications |
While both Asic Design and FPGA Design involve hardware description languages and digital logic, Asic Design focuses on creating custom chips for high-volume production, requiring detailed fabrication knowledge. FPGA Design emphasizes flexible, reprogrammable hardware for testing and prototyping. Understanding these differences helps professionals choose the right career path or project focus within the hardware design industry.
ASIC Design Engineer
Responsibilities:
Requirements:
Nice to Have:
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1 - 10 Employees
Mission Hills, CA, US
2013