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Asic Design Jobs in Washington, DC (NOW HIRING)

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Hardware Design Engineer 3

Fort George G Meade, MD · On-site

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Design and develop ASIC, FPGA, and SoC-based microelectronic systems * Perform simulation, verification, and debugging of hardware designs * Develop and maintain HDL code using Verilog and/or VHDL

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All JobsAsic Design JobsAsic Design Jobs in Washington, DC

Asic Design information

See Washington, DC salary details

$106.4K

$170K

$228.7K

How much do asic design jobs pay per year?

As of Aug 18, 2026, the average yearly pay for asic design in Washington, DC is $170,048.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,900.00 and $203,800.00 per year, depending on experience, location, and employer.

What is an ASIC designer?

ASIC designers are engineers who specialize in creating application-specific integrated circuits (ASICs), which are custom-designed semiconductor chips tailored for a particular use or product. They are responsible for designing, verifying, and testing hardware components at the microchip level to ensure optimal performance and efficiency. ASIC designers work closely with electronic design automation (EDA) tools, collaborate with software and hardware teams, and follow rigorous design cycles to meet project specifications. Their work is crucial in industries such as telecommunications, consumer electronics, automotive, and data centers where custom silicon solutions are required.

What are the key skills and qualifications needed to thrive as an ASIC design engineer?

To thrive as an ASIC Design Engineer, you need a solid background in digital design principles, hardware description languages (such as Verilog or VHDL), and a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence or Synopsys, as well as knowledge of simulation and verification methodologies, is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are crucial soft skills in this role. These competencies ensure accurate, efficient chip designs and smooth collaboration throughout complex development cycles.

What are some common challenges faced by ASIC design engineers during the chip development process?

ASIC Design Engineers often encounter challenges such as balancing power, performance, and area (PPA) constraints while meeting tight project deadlines. Debugging complex hardware issues during simulation and verification phases requires keen analytical skills and attention to detail. Collaboration with cross-functional teams—including verification, physical design, and test engineering—is essential to ensure design specifications are met and to address integration issues. Staying updated with evolving EDA tools and methodologies is also crucial for success in this fast-paced field.

What is the difference between Asic Design vs FPGA Design?

AspectAsic DesignFPGA Design
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; knowledge of VLSI designSimilar credentials; often requires knowledge of FPGA programming languages like VHDL/Verilog
Work EnvironmentDesigning custom chips in semiconductor labs or design housesImplementing and testing designs on FPGA boards in labs or development environments
Industry UsageUsed in high-volume, performance-critical applications like smartphones, serversUsed for prototyping, testing, and low to medium volume applications

While both Asic Design and FPGA Design involve hardware description languages and digital logic, Asic Design focuses on creating custom chips for high-volume production, requiring detailed fabrication knowledge. FPGA Design emphasizes flexible, reprogrammable hardware for testing and prototyping. Understanding these differences helps professionals choose the right career path or project focus within the hardware design industry.

How much do ASIC designers make?

ASIC designers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior ASIC designers with specialized skills or certifications can earn higher salaries, often exceeding $180,000. Compensation may also include bonuses and stock options in some organizations.

Is ASIC a good career?

ASIC design is a specialized field within electronics engineering focused on developing custom integrated circuits, often requiring knowledge of hardware description languages like VHDL or Verilog. It offers strong job prospects due to the demand for high-performance chips in various industries, and typically involves working in teams with engineers skilled in digital design, verification, and synthesis. The career can be rewarding for those with technical skills and an interest in semiconductor technology, but it may require continuous learning to keep up with evolving tools and industry standards.

Is ASIC design in demand?

ASIC design is in high demand due to the growth of specialized hardware in industries like consumer electronics, telecommunications, and automotive. Skilled ASIC designers with knowledge of hardware description languages such as VHDL or Verilog and experience with FPGA prototyping are sought after in the job market.

What are the most commonly searched types of Asic Design jobs in Washington, DC?

The most popular types of Asic Design jobs in Washington, DC are:

What are popular job titles related to Asic Design jobs in Washington, DC?

For Asic Design jobs in Washington, DC, the most frequently searched job titles are:

What job categories do people searching Asic Design jobs in Washington, DC look for?

The top searched job categories for Asic Design jobs in Washington, DC are:

Asic Design jobs near you
Infographic showing various Asic Design job openings in Washington, DC as of August 2026, with employment types broken down into 88% Full Time, 8% Part Time, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $170,048 per year, or $81.8 per hour.

Senior ASIC Physical Design Engineer

Johns Hopkins Applied Physics Lab

Laurel, MD • On-site

$105 - $290/hr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 13 days ago

Job description

Description

Do you love building and prototyping robust electrical systems?

Are you passionate about providing real impact to the country’s toughest national security problems?

If so, we're looking for someone like you to join our team at APL.

The Miniature Device Technologies Group develops highly customized tools and techniques required to carry out missions around the globe. Whether it be a quick reaction need from the field or the long‑term development of a novel capability, we work hand in hand with our government sponsors to conceive and realize solutions to their most challenging problems. We leverage our multi‑disciplinary set of capabilities in custom application‑specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field‑programmable gate array (FPGA), and signal processing design to create ultra‑small, low‑power solutions that exceed comparable commercial alternatives.

We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state‑of‑the‑art in miniature systems for a wide range of applications. In this role, you will be responsible for all back‑end flow aspects, including synthesis, top‑level floor‑planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks. You will be working closely with the ASIC design team to identify back‑end issues, and assist in addressing these issues, both in the RTL and gate‑level phases of the design. You will help explore process selection for new proposals and designs, assessing aspects such as achievable size and power, and availability of the necessary design features and intellectual property (IP.). Additionally, you will perform custom physical design as needed, both to complete custom block layouts, and to perform custom modifications necessary at the top level of the ASIC.

As a Senior ASIC Physical Design Engineer
  • Your primary responsibility will be digital back‑end flow, from synthesis to a completed, verified top‑level layout, ready for tapeout submission
  • You will contribute to process selection for new designs and proposals
  • You will floorplan the top‑level layout of the digital and mixed‑signal ASICs
  • You will perform timing analysis and design partitioning
  • You will perform SCAN and BIST insertion for maximum defect coverage
  • You will work with digital designers to debug and address back‑end related RTL and gate‑level issues
  • You will perform all physical verification, including DRC, DRC+, MCD, and LVS
  • You will perform custom physical layout
  • You may assist with ASIC design environment enhancements and scripting
  • You will demonstrate initiative by identifying and driving process improvements, and implementing innovative solutions to complex design challenges
  • You will build and maintain strong working relationships with cross‑functional teams, including digital design, verification, and software teams
  • You will provide leadership and guidance to junior physical design engineers, and contribute to their growth and development
  • You will collaborate with the team to achieve project goals and objectives, and drive results through effective teamwork and problem‑solving
  • You will foster open communication and collaboration with digital designers, junior physical design engineers, and other stakeholders to ensure seamless project execution
Qualifications

You meet our minimum qualifications for the job if you…

  • Possess an Associate’s degree in a technical field, or a combination of equivalent level experience/education/certifications.
  • Are skilled at using Cadence ASIC design tools for back‑end flow implementation
  • Are skilled at using Siemens Calibre physical verification tools
  • Have 6+ years of experience specifically performing back‑end ASIC design
  • Are able to obtain an Interim Secret level security clearance by your start date and can ultimately obtain a Secret level clearance. If selected, you will be subject to a government security clearance investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship.

You'll go above and beyond our minimum requirements if you…

  • Have experience with custom physical layout in Cadence Virtuoso
  • Are skilled at using Siemens ASIC design tools for back‑end flow implementation
  • Have extensive knowledge and experience in ASIC technology characterization for process selection
  • Hold an active clearance and/or have successfully undergone single‑scope background investigations in the past.
About Us

Why Work at APL?

The Johns Hopkins University Applied Physics Laboratory (APL) brings world‑class expertise to our nation’s most critical defense, security, space and science challenges. While we are dedicated to solving complex challenges and pioneering new technologies, what makes us truly outstanding is our culture. We offer a vibrant, welcoming atmosphere where you can bring your authentic self to work, continue to grow, and build strong connections with inspiring teammates.

At APL, we celebrate our differences of perspectives and encourage creativity and bold, new ideas. Our employees enjoy generous benefits, including a robust education assistance program, unparalleled retirement contributions, and a healthy work/life balance. APL’s campus is located in the Baltimore‑Washington metro area. Learn more about our career opportunities at https://www.jhuapl.edu/careers.

All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, physical or mental disability, genetic information, veteran status, occupation, marital or familial status, political opinion, personal appearance, or any other characteristic protected by applicable law. APL is committed to providing reasonable accommodation to individuals of all abilities, including those with disabilities. If you require a reasonable accommodation to participate in any part of the hiring process, please contact Accessibility@jhuapl.edu.

The referenced pay range is based on JHU APL’s good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign‑on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short‑term disability, long‑term disability, flexible spending accounts, education assistance, and training and development. Applications are accepted on a rolling basis.

Minimum Rate

$105,000 Annually

Maximum Rate

$290,000 Annually

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