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Asic Design Jobs in Washington, DC (NOW HIRING)

3B Staffing LLC

FPGA/ASIC Design Engineer

Reston, VA · On-site

$128K - $176.30K/yr

Technicall/Professional Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed ...

Next Step Systems

FPGA Electrical Engineer

Linthicum, MD · On-site

... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...

Next Step Systems

Senior FPGA Electrical Engineer

Linthicum, MD · On-site

$102.70K - $138.20K/yr

... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...

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$106.5K

$170.1K

$228.8K

How much do asic design jobs pay per year?

As of May 28, 2026, the average yearly pay for asic design in Washington, DC is $170,111.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,900.00 and $203,900.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC Design Engineer, and why are they important?

To thrive as an ASIC Design Engineer, you need a solid background in digital design principles, hardware description languages (such as Verilog or VHDL), and a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence or Synopsys, as well as knowledge of simulation and verification methodologies, is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are crucial soft skills in this role. These competencies ensure accurate, efficient chip designs and smooth collaboration throughout complex development cycles.

What are some common challenges faced by ASIC Design Engineers during the chip development process?

ASIC Design Engineers often encounter challenges such as balancing power, performance, and area (PPA) constraints while meeting tight project deadlines. Debugging complex hardware issues during simulation and verification phases requires keen analytical skills and attention to detail. Collaboration with cross-functional teams—including verification, physical design, and test engineering—is essential to ensure design specifications are met and to address integration issues. Staying updated with evolving EDA tools and methodologies is also crucial for success in this fast-paced field.

What are ASIC designers?

ASIC designers are engineers who specialize in creating application-specific integrated circuits (ASICs), which are custom-designed semiconductor chips tailored for a particular use or product. They are responsible for designing, verifying, and testing hardware components at the microchip level to ensure optimal performance and efficiency. ASIC designers work closely with electronic design automation (EDA) tools, collaborate with software and hardware teams, and follow rigorous design cycles to meet project specifications. Their work is crucial in industries such as telecommunications, consumer electronics, automotive, and data centers where custom silicon solutions are required.

What engineering jobs pay $500,000?

In the field of ASIC design and related engineering roles, senior positions such as principal engineer, engineering director, or VP of engineering can reach or exceed $500,000 annually, especially in high-cost-of-living areas or large tech companies. These roles typically require extensive experience, advanced skills in hardware design, and often involve leadership responsibilities and stock options.

What is the difference between Asic Design vs FPGA Design?

AspectAsic DesignFPGA Design
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; knowledge of VLSI designSimilar credentials; often requires knowledge of FPGA programming languages like VHDL/Verilog
Work EnvironmentDesigning custom chips in semiconductor labs or design housesImplementing and testing designs on FPGA boards in labs or development environments
Industry UsageUsed in high-volume, performance-critical applications like smartphones, serversUsed for prototyping, testing, and low to medium volume applications

While both Asic Design and FPGA Design involve hardware description languages and digital logic, Asic Design focuses on creating custom chips for high-volume production, requiring detailed fabrication knowledge. FPGA Design emphasizes flexible, reprogrammable hardware for testing and prototyping. Understanding these differences helps professionals choose the right career path or project focus within the hardware design industry.

What are the most commonly searched types of Asic Design jobs in Washington, DC? The most popular types of Asic Design jobs in Washington, DC are:
What are popular job titles related to Asic Design jobs in Washington, DC? For Asic Design jobs in Washington, DC, the most frequently searched job titles are:
What job categories do people searching Asic Design jobs in Washington, DC look for? The top searched job categories for Asic Design jobs in Washington, DC are:
Asic Design jobs near you
Infographic showing various Asic Design job openings in Washington, DC as of May 2026, with employment types broken down into 100% Full Time. Highlights an 79% In-person, 14% Hybrid, and 7% Remote job distribution, with an average salary of $170,111 per year, or $81.8 per hour.
FPGA/ASIC Design Engineer

FPGA/ASIC Design Engineer

3B Staffing LLC

Reston, VA • On-site

$128K - $176.30K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Job Category:
Technicall/Professional
Job Description:
Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.
L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).
This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.
Skills/Experience:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
Possess an active SECRET Clearance
Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
Proficient in VHDL design process and FPGA flow
Knowledge of Ethernet, TCP/IP protocols
Strong logic/board debug, and analytical skills.
Excellent written, verbal, and presentation skills.
A PLUS for prior experience with:
High Level Synthesis (HLS) with Vivado,
Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
VHDL Experience is required for all candidates to be considered.
  • Looking for mid-senior level folks
  • Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
  • Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
  • Big Plus
    • Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
    • Mentor EDA CDC/Lint/AC/RDC

Required Skills:
Derive engineering specifications from system requirements and develop detailed architecture
Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
Generate test plans
Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
Silicon/FPGA bring up, characterization and production ramp/support/collateral
Desired Skills:
Prior experience in Aerospace / Defense
Experience in C++ (OOP)
Experience in Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).
Experience with Universal Verification Mythology (UVM)
Experience with project leadership and EVM
Degree Requirements:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.

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