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Asic Design Jobs (NOW HIRING)

Credo, Inc

Director, ASIC Design

San Jose, CA · On-site

$210K - $240K/yr

About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions for next-generation data communication products. In this role, you will be responsible for driving ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block * Collaborate with ...

Credo, Inc

Director, ASIC Design

San Jose, CA · On-site

$210K - $240K/yr

About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions for next-generation data communication products. In this role, you will be responsible for driving ...

Marvell

Senior Manager, ASIC Design

Santa Clara, CA · On-site

What You Can Expect We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee ...

Kratos Defense

ASIC Design Leader

Crane, IN

... of ASIC development * 2+ years of design implementation and verification using Verilog/VHDL * 5+ years of experience with FPGAs with knowledge of Verilog/VHDL * 5+ years of experience with testing ...

Credo, Inc

Principal ASIC Design Engineer

San Jose, CA · On-site

$180K - $210K/yr

About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · Hybrid

NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company ...

Ayar Labs

Sr. Engineer, ASIC Design

San Jose, CA

$160K - $192K/yr

Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...

Credo, Inc

Principal ASIC Design Engineer

San Jose, CA · On-site

$180K - $210K/yr

About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will ...

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All JobsAsic Design Jobs

Asic Design information

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$94K

$150.2K

$202K

How much do asic design jobs pay per year?

As of Jun 18, 2026, the average yearly pay for asic design in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC Design Engineer, and why are they important?

To thrive as an ASIC Design Engineer, you need a solid background in digital design principles, hardware description languages (such as Verilog or VHDL), and a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence or Synopsys, as well as knowledge of simulation and verification methodologies, is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are crucial soft skills in this role. These competencies ensure accurate, efficient chip designs and smooth collaboration throughout complex development cycles.

What is the difference between Asic Design vs FPGA Design?

AspectAsic DesignFPGA Design
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; knowledge of VLSI designSimilar credentials; often requires knowledge of FPGA programming languages like VHDL/Verilog
Work EnvironmentDesigning custom chips in semiconductor labs or design housesImplementing and testing designs on FPGA boards in labs or development environments
Industry UsageUsed in high-volume, performance-critical applications like smartphones, serversUsed for prototyping, testing, and low to medium volume applications

While both Asic Design and FPGA Design involve hardware description languages and digital logic, Asic Design focuses on creating custom chips for high-volume production, requiring detailed fabrication knowledge. FPGA Design emphasizes flexible, reprogrammable hardware for testing and prototyping. Understanding these differences helps professionals choose the right career path or project focus within the hardware design industry.

How hard is it to get into ASIC design?

Getting into ASIC design typically requires a strong background in electrical engineering or computer engineering, proficiency in hardware description languages like VHDL or Verilog, and experience with EDA tools. Entry-level positions often seek candidates with relevant internships or project experience, and advanced roles may require specialized knowledge or certifications. The field is competitive but accessible with the right technical skills and education.

Is ASIC design in demand?

ASIC design is in high demand due to the growth of specialized hardware for applications like AI, 5G, and IoT. Professionals with skills in hardware description languages such as VHDL or Verilog, and experience with FPGA prototyping, are particularly sought after in the industry.

How much does an ASIC design engineer make?

An ASIC design engineer's salary typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $180,000.

What are some common challenges faced by ASIC Design Engineers during the chip development process?

ASIC Design Engineers often encounter challenges such as balancing power, performance, and area (PPA) constraints while meeting tight project deadlines. Debugging complex hardware issues during simulation and verification phases requires keen analytical skills and attention to detail. Collaboration with cross-functional teams—including verification, physical design, and test engineering—is essential to ensure design specifications are met and to address integration issues. Staying updated with evolving EDA tools and methodologies is also crucial for success in this fast-paced field.

What are ASIC designers?

ASIC designers are engineers who specialize in creating application-specific integrated circuits (ASICs), which are custom-designed semiconductor chips tailored for a particular use or product. They are responsible for designing, verifying, and testing hardware components at the microchip level to ensure optimal performance and efficiency. ASIC designers work closely with electronic design automation (EDA) tools, collaborate with software and hardware teams, and follow rigorous design cycles to meet project specifications. Their work is crucial in industries such as telecommunications, consumer electronics, automotive, and data centers where custom silicon solutions are required.

What engineers make $500,000?

Senior engineers in specialized fields such as software engineering, data engineering, or hardware design can earn $500,000 or more annually, especially with extensive experience, advanced skills, and in high-demand industries like technology or finance. Compensation often includes base salary, bonuses, and stock options, particularly at senior or executive levels.
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Asic Design jobs near you
Senior Manager, ASIC Design

Senior Manager, ASIC Design

Marvell Technology, Inc.

Santa Clara, CA • On-site

Full-time

Life, Retirement

Posted 2 days ago

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
What You Can Expect
We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project delivery, and alignment with company goals.
This role demands proven technical expertise in advanced ASIC design flows and leadership in execution, scheduling, cross-functional coordination, and final product delivery.
What We're Looking For
  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
  • 8+ years of ASIC/SOC digital design experience
  • 3+ years of people management experience
  • Excellent leadership, communication, team building and stakeholder management skills
  • Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints
  • Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies
  • Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies
  • Hands on design experience in one or more industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink etc
  • Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)
  • Proficiency with front end development tools/methodologies, and scripting for automation and flow integration

Expected Base Pay Range (USD)
161,600 - 239,210, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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