ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Senior Manager, ASIC Design Engineering
San Jose, CA · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Senior Manager, ASIC Design Engineering
San Jose, CA · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
ASIC Design Engineer
San Diego, CA · On-site
Contribute to ASIC development activities including RTL design, static timing analysis, timing ... Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.Strong ...
ASIC Design Engineer
San Diego, CA · On-site
Contribute to ASIC development activities including RTL design, static timing analysis, timing ... Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.Strong ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...
Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
ASIC / VLSI Engineers
Milpitas, CA · On-site
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
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ASIC / VLSI Engineers
Milpitas, CA · On-site
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and ... We need an RTL designer who understands that correctness has to be established through rigorous ...
We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and ... We need an RTL designer who understands that correctness has to be established through rigorous ...
RTL Engineer (Ethernet)
San Francisco, CA · On-site
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...
New
RTL Engineer (Ethernet)
San Francisco, CA · On-site
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...
New
Senior ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$142K - $150K/yr
Responsibilities for this Position We're looking for an Advanced ASIC Design Engineer with solid ... We need an RTL designer who understands that correctness has to be established through rigorous ...
Senior ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$142K - $150K/yr
Responsibilities for this Position We're looking for an Advanced ASIC Design Engineer with solid ... We need an RTL designer who understands that correctness has to be established through rigorous ...
RTL Design Engineer
Reading, MA · On-site
$123K - $196K/yr
... ASIC Group is responsible for developing advanced node ASICs for Teradyne next‑generation ... Responsibilities * Develop specifications, micro‑architecture, and RTL design of ...
RTL Design Engineer
Reading, MA · On-site
$123K - $196K/yr
... ASIC Group is responsible for developing advanced node ASICs for Teradyne next‑generation ... Responsibilities * Develop specifications, micro‑architecture, and RTL design of ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
Temporary Asic Rtl Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do temporary asic rtl design engineer jobs pay per year?
As of Sep 10, 2026, the average yearly pay for temporary asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
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States with the most job openings for Temporary Asic Rtl Design Engineer jobs include:
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Senior ASIC Design Engineer
San Francisco, CA • On-site
Ethan Alexander Group •
Recruiting and Staffing Services • 1 - 10 employees1 - 10 employees
Full-time
Re-posted 13 days ago
Job description
ASIC Design Engineer
Responsibilities:
- Define and bring up FPGA platforms for pre-silicon validation and software development
- Map ASIC RTL to FGPA while minimizing code base differences
- Create and execute test plans for validating SoC functionality and performance
- Resolve challenging system level issues that span multiple disciplines
- Design logic starting from specification or high level feature description
Requirements:
- Minimum of 5 years of relevant experience.
- Scripting or programming experience in Python or C/C++
- Ability to write and analyze the completeness of constraints
- Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters
- Strong analytical and debugging skills
- BS in Electrical Engineering or equivalent required, MS preferred
Nice to Have:
- Familiarity with Xilinx FPGA’s and Vivado tool chain
- Experience with validating and debugging low-power wireless systems
- Understanding of common interfaces and bus protocols (e.g. I2C, SPI, AHB)
- Knowledge of wireless protocols (e.g. Bluetooth Low Energy)
About Ethan Alexander Group
Sourced by ZipRecruiter
Industry
Recruiting and staffing services
Company size
1 - 10 Employees
Headquarters location
Mission Hills, CA, US
Year founded
2013