Richardson, TX · On-site +1
$122K/yr
This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...
Richardson, TX · On-site +1
$122K/yr
This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...
Richardson, TX · On-site
$125 - $150/hr
This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...
Richardson, TX · On-site
$125 - $150/hr
This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...
San Jose, CA · On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple ...
San Jose, CA · On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple ...
San Jose, CA · On-site
$200 - $250/hr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from ... You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple ...
San Jose, CA · On-site
$200 - $250/hr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from ... You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple ...
Austin, TX · Hybrid
$198K - $268K/yr
Experience with System Verilog RTL design, coupled with design synthesis. * Experience with lint ... Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to ...
Austin, TX · Hybrid
$198K - $268K/yr
Experience with System Verilog RTL design, coupled with design synthesis. * Experience with lint ... Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to ...
Austin, TX · On-site
$198K - $268K/yr
Experience with System Verilog RTL design, coupled with design synthesis. * Experience with lint ... Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to ...
Austin, TX · On-site
$198K - $268K/yr
Experience with System Verilog RTL design, coupled with design synthesis. * Experience with lint ... Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to ...
San Jose, CA · On-site
$144K - $198K/yr
FPGA / RTL Design Engineer Location: San Jose, CA FPGA/RTL Design Engineer to design, implement ... Develop RTL code (Verilog, VHDL, SystemVerilog) for FPGA and digital circuits, integrating IP and ...
San Jose, CA · On-site
$144K - $198K/yr
FPGA / RTL Design Engineer Location: San Jose, CA FPGA/RTL Design Engineer to design, implement ... Develop RTL code (Verilog, VHDL, SystemVerilog) for FPGA and digital circuits, integrating IP and ...
Richardson, TX · On-site +1
$122K - $149K/yr
The ideal candidate will bring strong Verilog RTL design experience, hands-on digital and AMS ... Work closely with cross-functional engineering teams to support successful silicon development and ...
Richardson, TX · On-site +1
$122K - $149K/yr
The ideal candidate will bring strong Verilog RTL design experience, hands-on digital and AMS ... Work closely with cross-functional engineering teams to support successful silicon development and ...
Milpitas, CA · On-site
$158K/yr
Digital Design Engineer focusing on high-performance analog-to-digital and digital-to-analog ... Hands on experience with the Verilog RTL coding including state machines, adders, multipliers ...
Milpitas, CA · On-site
$158K/yr
Digital Design Engineer focusing on high-performance analog-to-digital and digital-to-analog ... Hands on experience with the Verilog RTL coding including state machines, adders, multipliers ...
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Verilog #VLSI #CDC #STA #Synthesis #DFT #Python #TCL #AMBA #PCIe #LowPowerDesign to contribute ...
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Verilog #VLSI #CDC #STA #Synthesis #DFT #Python #TCL #AMBA #PCIe #LowPowerDesign to contribute ...
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Verilog #VLSI #CDC #STA #Synthesis #DFT #Python #TCL #AMBA #PCIe #LowPowerDesign to contribute ...
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Verilog #VLSI #CDC #STA #Synthesis #DFT #Python #TCL #AMBA #PCIe #LowPowerDesign to contribute ...
Austin, TX · On-site
$134K/yr
Digital Design Engineer focusing on high-performance analog-to-digital and digital-to-analog ... Hands on experience with the Verilog RTL coding including state machines, adders, multipliers ...
Austin, TX · On-site
$134K/yr
Digital Design Engineer focusing on high-performance analog-to-digital and digital-to-analog ... Hands on experience with the Verilog RTL coding including state machines, adders, multipliers ...
Cary, NC · On-site
Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ... Engineering.
Cary, NC · On-site
Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ... Engineering.
Melbourne, FL · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ...
Melbourne, FL · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ...
Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ... Engineering.
Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ... Engineering.
Waltham, MA · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ...
Waltham, MA · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ...
Cary, NC · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ...
Cary, NC · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ...
$134K/yr
... RTL Design Engineer. This is an exciting position in the world class Apple mixed-signal silicon ... Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal ...
$134K/yr
... RTL Design Engineer. This is an exciting position in the world class Apple mixed-signal silicon ... Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal ...
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ...
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Preferred Qualifications Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge ...
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
| Aspect | Verilog Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Primary Focus | Designing and implementing RTL code using Verilog for digital circuits | Designing digital systems, including RTL, FPGA, and ASIC components |
| Skills & Certifications | Verilog proficiency, FPGA/ASIC knowledge, hardware description languages | Digital logic, HDL skills, FPGA/ASIC experience |
| Work Environment | Semiconductor companies, hardware design firms, R&D labs | Electronics companies, chip design firms, embedded systems |
While both roles involve digital hardware design, a Verilog Rtl Design Engineer specializes specifically in writing RTL code in Verilog, whereas a Digital Design Engineer may work across broader digital system design, including RTL, FPGA, and ASIC development. The Verilog Rtl Design Engineer role is more focused on HDL coding, while the Digital Design Engineer may encompass a wider range of digital design tasks.
For Verilog Rtl Design Engineer jobs, the most frequently searched job titles are:
Richardson, TX • On-site, Remote
$122K/yr
Full-time
Posted 28 days ago
Develop, integrate, and debug Verilog/SystemVerilog RTL for digital blocks, processing logic, control logic, interfaces, and mixed-signal IC subsystems
Translate architecture, system, and product requirements into RTL implementations and support block-level and subsystem-level integration
Collaborate with verification, analog/mixed-signal, physical design, and product engineering teams to support silicon development and delivery
Sourced by ZipRecruiter
Semiconductor and electronic component manufacturing
51 - 200 Employees
Dallas, TX, US
2004
