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Locum Asic Rtl Design Engineer Jobs (NOW HIRING)

... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...

ASIC Design Engineer

San Diego, CA · On-site

$99 - $148/hr

Contribute to ASIC development activities including RTL design, static timing analysis, timing ... Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.Strong ...

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...

TPU RTL Design Engineer

Sunnyvale, CA · On-site

$159K/yr

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Showing results 41-60

Locum Asic Rtl Design Engineer information

See salary details

$94K

$150.2K

$202K

How much do locum asic rtl design engineer jobs pay per year?

As of Aug 25, 2026, the average yearly pay for locum asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

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Infographic showing various Locum Asic Rtl Design Engineer job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

ML ASIC Design Engineer

Mountain View, NY • Hybrid

Waymo
Internet and IT • 1 - 5K employees

Full-time

Posted 16 days ago


Job description

Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.

This role follows a hybrid work schedule and you will report to the Senior Staff Silicon Engineer.

You will:

  • Work with researchers and architects to translate high level requirements into hardware features
  • Specify and design microarchitectures to deliver world class ML performance
  • Perform power, area and performance exploration and optimization of digital ASIC designs
  • Design high performance execution units, arithmetic circuits and programmable engines
  • Work with verification teams to guarantee functional correctness and performance

You have:

  • BS degree in Computer Engineering or equivalent practical experience
  • 5+ years of industry experience with SystemVerilog, ASIC RTL design and microarchitecture
  • 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU)
  • Fluency in at least one high level programming language such as Python, C++

We prefer:

  • Experience designing datapath elements of high performance cores (CPU/GPU/NPU)
  • Experience working with Chisel (Scala) or other higher-level hardware DSL's
  • Working knowledge of machine learning algorithms & how they map to hardware
  • Familiarity with Synthesis and power analysis tools
  • Experience working with formal tools for datapath verification