... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
ASIC Design Engineer
San Diego, CA · On-site
$99 - $148/hr
Contribute to ASIC development activities including RTL design, static timing analysis, timing ... Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.Strong ...
ASIC Design Engineer
San Diego, CA · On-site
$99 - $148/hr
Contribute to ASIC development activities including RTL design, static timing analysis, timing ... Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.Strong ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
SrvDigital Design Engineer Boise, Idaho, United States of America
Boise, ID · On-site
$120 - $180/hr
Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...
SrvDigital Design Engineer Boise, Idaho, United States of America
Boise, ID · On-site
$120 - $180/hr
Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Staff ASIC Design Engineer
Saint Paul, MN · On-site
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
Staff ASIC Design Engineer
Saint Paul, MN · On-site
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Quick apply
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and ... We need an RTL designer who understands that correctness has to be established through rigorous ...
We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and ... We need an RTL designer who understands that correctness has to be established through rigorous ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Senior ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$142K - $150K/yr
Responsibilities for this Position We're looking for an Advanced ASIC Design Engineer with solid ... We need an RTL designer who understands that correctness has to be established through rigorous ...
Senior ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$142K - $150K/yr
Responsibilities for this Position We're looking for an Advanced ASIC Design Engineer with solid ... We need an RTL designer who understands that correctness has to be established through rigorous ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
Principal ASIC Design Engineer
Saint Paul, MN · On-site
$200K - $220K/yr
Job SummaryWe are currently seeking a Principal ASIC Design Engineer responsible for developing ... Writing Register Transfer Level (RTL) code using industry standard hardware description languages.
Principal ASIC Design Engineer
Saint Paul, MN · On-site
$200K - $220K/yr
Job SummaryWe are currently seeking a Principal ASIC Design Engineer responsible for developing ... Writing Register Transfer Level (RTL) code using industry standard hardware description languages.
RTL Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$145K - $195K/yr
RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level ...
RTL Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$145K - $195K/yr
RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level ...
ASIC Design and Integration Engineer
$129K - $194K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
ASIC Design and Integration Engineer
$129K - $194K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Locum Asic Rtl Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do locum asic rtl design engineer jobs pay per year?
What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?
| Aspect | Locum Asic Rtl Design Engineer | Contract Asic Rtl Design Engineer |
|---|---|---|
| Credentials | Typically requires relevant engineering degrees and RTL design experience | Similar credentials, often with specific RTL design certifications |
| Work Environment | Temporary, short-term assignments often in multiple locations | Project-based roles, usually in a fixed location or remote |
| Employer Usage | Used by agencies or companies needing immediate, short-term expertise | Engaged by companies or staffing agencies for project-specific work |
Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.
What cities are hiring for Locum Asic Rtl Design Engineer jobs?
Cities with the most Locum Asic Rtl Design Engineer job openings:
What are the most commonly searched types of Asic Rtl Design Engineer jobs?
The most popular types of Asic Rtl Design Engineer jobs are:
What states have the most Locum Asic Rtl Design Engineer jobs?
States with the most job openings for Locum Asic Rtl Design Engineer jobs include:
What job categories do people searching Locum Asic Rtl Design Engineer jobs look for?
The top searched job categories for Locum Asic Rtl Design Engineer jobs are:

ML ASIC Design Engineer
Mountain View, NY • Hybrid
Full-time
Posted 16 days ago
Job description
Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.
This role follows a hybrid work schedule and you will report to the Senior Staff Silicon Engineer.
You will:
- Work with researchers and architects to translate high level requirements into hardware features
- Specify and design microarchitectures to deliver world class ML performance
- Perform power, area and performance exploration and optimization of digital ASIC designs
- Design high performance execution units, arithmetic circuits and programmable engines
- Work with verification teams to guarantee functional correctness and performance
You have:
- BS degree in Computer Engineering or equivalent practical experience
- 5+ years of industry experience with SystemVerilog, ASIC RTL design and microarchitecture
- 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU)
- Fluency in at least one high level programming language such as Python, C++
We prefer:
- Experience designing datapath elements of high performance cores (CPU/GPU/NPU)
- Experience working with Chisel (Scala) or other higher-level hardware DSL's
- Working knowledge of machine learning algorithms & how they map to hardware
- Familiarity with Synthesis and power analysis tools
- Experience working with formal tools for datapath verification
About Waymo
Sourced by ZipRecruiter
Industry
Internet and it
Company size
1,001 - 5,000 Employees
Headquarters location
Mountain View, CA, US
Year founded
2009