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Locum Asic Rtl Design Engineer Jobs (NOW HIRING)

Contribute to ASIC development activities including RTL design, static timing analysis, timing ... Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.Strong ...

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...

... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...

Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...

New

RTL Design Engineer

Reading, MA · On-site

$123K - $196K/yr

... ASIC Group is responsible for developing advanced node ASICs for Teradyne next‑generation ... Responsibilities * Develop specifications, micro‑architecture, and RTL design of ...

Showing results 41-60

Locum Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do locum asic rtl design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for locum asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

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Infographic showing various Locum Asic Rtl Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Senior ASIC Design Engineer

San Francisco, CA • On-site

Ethan Alexander Group
Recruiting and Staffing Services • 1 - 10 employees

Full-time

Re-posted 13 days ago


Job description

ASIC Design Engineer


Responsibilities:


  • Define and bring up FPGA platforms for pre-silicon validation and software development
  • Map ASIC RTL to FGPA while minimizing code base differences
  • Create and execute test plans for validating SoC functionality and performance
  • Resolve challenging system level issues that span multiple disciplines
  • Design logic starting from specification or high level feature description


Requirements:


  • Minimum of 5 years of relevant experience.
  • Scripting or programming experience in Python or C/C++
  • Ability to write and analyze the completeness of constraints
  • Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters
  • Strong analytical and debugging skills
  • BS in Electrical Engineering or equivalent required, MS preferred


Nice to Have:


  • Familiarity with Xilinx FPGA’s and Vivado tool chain
  • Experience with validating and debugging low-power wireless systems
  • Understanding of common interfaces and bus protocols (e.g. I2C, SPI, AHB)
  • Knowledge of wireless protocols (e.g. Bluetooth Low Energy)