Locum Asic Rtl Design Engineer Jobs (NOW HIRING)

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
• Design experience optimizing for performance, power, and area.
• Experience with digital design fundamentals and microarchitecture design.
• Experience working cross-functionally with DV and PD teams.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 4 years of RTL design experience.
• Experience with Linting, CDC, RDC, LEC.
• Experience with Scripting languages (i.e. Python or Perl).
• Experience with integration.
• Experience optimizing RTL solutions, RTL design methodologies and automate front-end engineering flows.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including verification, physical design, validation, and firmware, to deliver hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows.
As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $198000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities

• Define and document complex microarchitecture for the TPU, writing high-quality, performant, and power-efficient RTL code primarily in SystemVerilog.
• Partner with cross-functional teams to drive block-level and chip-level integration efforts for the machine learning accelerators.
• Collaborate closely with the verification team to develop robust test plans, debug RTL, and guarantee overall functional correctness.
• Support post-silicon validation and debugging efforts while contributing to the continuous enhancement of internal design tools, flows, and methodologies.
• Work closely with the physical design team to meet timing, area, power, and manufacturability requirements.

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